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Searched refs:hwsp_offset (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/i915/gt/
Dintel_timeline.c61 u32 ofs = offset_in_page(timeline->hwsp_offset); in intel_timeline_pin_map()
86 timeline->hwsp_offset = offset; in intel_timeline_init()
97 timeline->hwsp_seqno = (void *)(long)timeline->hwsp_offset; in intel_timeline_init()
99 GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size); in intel_timeline_init()
208 tl->hwsp_offset = in intel_timeline_pin()
210 offset_in_page(tl->hwsp_offset); in intel_timeline_pin()
212 tl->fence_context, tl->hwsp_offset); in intel_timeline_pin()
311 u32 next_ofs = offset_in_page(tl->hwsp_offset + TIMELINE_SEQNO_BYTES); in __intel_timeline_get_seqno()
317 tl->hwsp_offset = i915_ggtt_offset(tl->hwsp_ggtt) + next_ofs; in __intel_timeline_get_seqno()
Dgen8_engine_cs.c340 static u32 hwsp_offset(const struct i915_request *rq) in hwsp_offset() function
349 return page_mask_bits(tl->hwsp_offset) + offset_in_page(rq->hwsp_seqno); in hwsp_offset()
365 *cs++ = hwsp_offset(rq); in gen8_emit_init_breadcrumb()
575 return gen8_emit_ggtt_write(cs, rq->fence.seqno, hwsp_offset(rq), 0); in emit_xcs_breadcrumb()
594 hwsp_offset(rq), in gen8_emit_fini_breadcrumb_rcs()
605 hwsp_offset(rq), in gen11_emit_fini_breadcrumb_rcs()
736 hwsp_offset(rq), in gen12_emit_fini_breadcrumb_rcs()
Dselftest_timeline.c39 return (address + offset_in_page(tl->hwsp_offset)) / TIMELINE_SEQNO_BYTES; in hwsp_cacheline()
509 err = emit_ggtt_store_dw(rq, tl->hwsp_offset, value); in checked_tl_write()
586 n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno); in live_hwsp_engine()
658 n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno); in live_hwsp_alternate()
718 seqno[0], tl->hwsp_offset); in live_hwsp_wrap()
720 err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[0]); in live_hwsp_wrap()
735 seqno[1], tl->hwsp_offset); in live_hwsp_wrap()
737 err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[1]); in live_hwsp_wrap()
1388 tl->hwsp_offset, *tl->hwsp_seqno); in live_hwsp_recycle()
Dintel_timeline_types.h49 u32 hwsp_offset; member
Dintel_timeline.h82 u32 *hwsp_offset);
Dselftest_rc6.c148 *cs++ = ce->timeline->hwsp_offset + 8; in __live_rc6_ctx()
Dselftest_engine_cs.c59 *cs++ = tl->hwsp_offset + slot * sizeof(u32); in write_timestamp()
Dintel_engine_cs.c1854 tl ? tl->hwsp_offset : 0, in print_ring()
2146 tl->hwsp_offset); in engine_dump_request()
/linux-6.1.9/drivers/gpu/drm/i915/selftests/
Di915_request.c1947 static u32 hwsp_offset(const struct intel_context *ce, u32 *dw) in hwsp_offset() function
1956 const u32 offset = hwsp_offset(ce, sema); in measure_semaphore_response()
2031 const u32 offset = hwsp_offset(ce, sema); in measure_idle_dispatch()
2102 const u32 offset = hwsp_offset(ce, sema); in measure_busy_dispatch()
2205 const u32 offset = hwsp_offset(ce, sema); in measure_inter_request()
2296 const u32 offset = hwsp_offset(ce, sema); in measure_context_switch()
2390 const u32 offset = hwsp_offset(ce, sema); in measure_preemption()
2510 const u32 offset = hwsp_offset(ce, sema); in measure_completion()
/linux-6.1.9/drivers/gpu/drm/i915/
Di915_request.h691 page_mask_bits(i915_request_active_timeline(rq)->hwsp_offset); in i915_request_active_seqno()
Di915_request.c1152 u32 hwsp_offset; in __emit_semaphore_wait() local
1160 err = intel_timeline_read_hwsp(from, to, &hwsp_offset); in __emit_semaphore_wait()
1186 *cs++ = hwsp_offset; in __emit_semaphore_wait()
/linux-6.1.9/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_submission.c4969 i915_request_active_timeline(rq)->hwsp_offset, in emit_fini_breadcrumb_parent_no_preempt_mid_batch()
5045 i915_request_active_timeline(rq)->hwsp_offset, in emit_fini_breadcrumb_child_no_preempt_mid_batch()