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Searched refs:hubp (Results 1 – 25 of 45) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/hw/
Dhubp.h57 struct hubp { struct
97 struct hubp *hubp,
104 struct hubp *hubp,
108 void (*dcc_control)(struct hubp *hubp, bool enable,
112 struct hubp *hubp,
117 struct hubp *hubp,
122 struct hubp *hubp,
128 struct hubp *hubp,
132 struct hubp *hubp,
136 struct hubp *hubp,
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubp.h31 #define TO_DCN20_HUBP(hubp)\ argument
32 container_of(hubp, struct dcn20_hubp, base)
257 struct hubp base;
273 struct hubp *hubp,
277 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
281 struct hubp *hubp,
284 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
292 struct hubp *hubp,
296 struct hubp *hubp,
300 bool hubp2_dmdata_status_done(struct hubp *hubp);
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Ddcn20_hubp.c45 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, in hubp2_set_vm_system_aperture_settings() argument
48 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp2_set_vm_system_aperture_settings()
80 struct hubp *hubp, in hubp2_program_deadline() argument
84 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp2_program_deadline()
170 void hubp2_vready_at_or_After_vsync(struct hubp *hubp, in hubp2_vready_at_or_After_vsync() argument
174 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp2_vready_at_or_After_vsync()
195 static void hubp2_program_requestor(struct hubp *hubp, in hubp2_program_requestor() argument
198 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp2_program_requestor()
228 struct hubp *hubp, in hubp2_setup() argument
238 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); in hubp2_setup()
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Ddcn20_hwseq.c183 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) in dcn20_set_flip_control_gsl()
184 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( in dcn20_set_flip_control_gsl()
185 pipe_ctx->plane_res.hubp, flip_immediate); in dcn20_set_flip_control_gsl()
270 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_triple_buffer()
271 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( in dcn20_program_triple_buffer()
272 pipe_ctx->plane_res.hubp, in dcn20_program_triple_buffer()
574 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn20_plane_atomic_disable() local
587 hubp->funcs->hubp_clk_cntl(hubp, false); in dcn20_plane_atomic_disable()
591 hubp->power_gated = true; in dcn20_plane_atomic_disable()
595 pipe_ctx->plane_res.hubp); in dcn20_plane_atomic_disable()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubp.c41 void hubp1_set_blank(struct hubp *hubp, bool blank) in hubp1_set_blank() argument
43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); in hubp1_set_blank()
65 hubp->mpcc_id = 0xf; in hubp1_set_blank()
66 hubp->opp_id = OPP_ID_INVALID; in hubp1_set_blank()
70 static void hubp1_disconnect(struct hubp *hubp) in hubp1_disconnect() argument
72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); in hubp1_disconnect()
81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp) in hubp1_disable_control() argument
83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); in hubp1_disable_control()
90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp) in hubp1_get_underflow_status() argument
93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); in hubp1_get_underflow_status()
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Ddcn10_hubp.h30 #define TO_DCN10_HUBP(hubp)\ argument
31 container_of(hubp, struct dcn10_hubp, base)
696 struct hubp base;
704 struct hubp *hubp,
714 struct hubp *hubp,
719 struct hubp *hubp,
723 struct hubp *hubp,
727 struct hubp *hubp,
733 struct hubp *hubp,
738 struct hubp *hubp,
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Ddcn10_hw_sequencer.c176 struct hubp *hubp = pool->hubps[i]; in dcn10_log_hubp_states() local
177 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state); in dcn10_log_hubp_states()
179 hubp->funcs->hubp_read_state(hubp); in dcn10_log_hubp_states()
183 hubp->inst, in dcn10_log_hubp_states()
537 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_did_underflow_occur() local
545 if (hubp->funcs->hubp_get_underflow_status(hubp)) { in dcn10_did_underflow_occur()
546 hubp->funcs->hubp_clear_underflow(hubp); in dcn10_did_underflow_occur()
754 struct hubp *hubp = dc->res_pool->hubps[0]; in undo_DEGVIDCN10_253_wa() local
759 hubp->funcs->set_blank(hubp, true); in undo_DEGVIDCN10_253_wa()
774 struct hubp *hubp = dc->res_pool->hubps[0]; in apply_DEGVIDCN10_253_wa() local
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Ddcn10_hw_sequencer_debug.c134 struct hubp *hubp = pool->hubps[i]; in dcn10_get_hubp_states() local
135 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state); in dcn10_get_hubp_states()
137 hubp->funcs->hubp_read_state(hubp); in dcn10_get_hubp_states()
144 hubp->inst, in dcn10_get_hubp_states()
163 hubp->inst, in dcn10_get_hubp_states()
510 struct hubp *hubp = pool->hubps[i]; in dcn10_clear_hubp_underflow() local
511 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state); in dcn10_clear_hubp_underflow()
513 hubp->funcs->hubp_read_state(hubp); in dcn10_clear_hubp_underflow()
516 hubp->funcs->hubp_clear_underflow(hubp); in dcn10_clear_hubp_underflow()
Ddcn10_hw_sequencer.h190 struct hubp *hubp);
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_hubp.c43 struct hubp *hubp, in hubp201_program_surface_config() argument
52 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp201_program_surface_config()
53 hubp1_program_tiling(hubp, tiling_info, format); in hubp201_program_surface_config()
54 hubp1_program_size(hubp, format, plane_size, dcc); in hubp201_program_surface_config()
55 hubp1_program_pixel_format(hubp, format); in hubp201_program_surface_config()
59 struct hubp *hubp, in hubp201_program_deadline() argument
63 hubp1_program_deadline(hubp, dlg_attr, ttu_attr); in hubp201_program_deadline()
66 static void hubp201_program_requestor(struct hubp *hubp, in hubp201_program_requestor() argument
69 struct dcn201_hubp *hubp201 = TO_DCN201_HUBP(hubp); in hubp201_program_requestor()
96 struct hubp *hubp, in hubp201_setup() argument
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Ddcn201_hwseq.c146 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( in dcn201_update_plane_addr()
147 pipe_ctx->plane_res.hubp, in dcn201_update_plane_addr()
317 struct hubp *hubp = res_pool->hubps[i]; in dcn201_init_hw() local
323 pipe_ctx->plane_res.hubp = hubp; in dcn201_init_hw()
326 hubp->mpcc_id = dpp->inst; in dcn201_init_hw()
327 hubp->opp_id = OPP_ID_INVALID; in dcn201_init_hw()
328 hubp->power_gated = false; in dcn201_init_hw()
331 hubp->funcs->hubp_init(hubp); in dcn201_init_hw()
356 pipe_ctx->plane_res.hubp = NULL; in dcn201_init_hw()
392 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_plane_atomic_disconnect() local
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Ddcn201_hubp.h32 #define TO_DCN201_HUBP(hubp)\ argument
33 container_of(hubp, struct dcn201_hubp, base)
117 struct hubp base;
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hubp.c45 void hubp3_set_vm_system_aperture_settings(struct hubp *hubp, in hubp3_set_vm_system_aperture_settings() argument
48 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp3_set_vm_system_aperture_settings()
73 struct hubp *hubp, in hubp3_program_surface_flip_and_addr() argument
77 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp3_program_surface_flip_and_addr()
318 hubp->request_address = *address; in hubp3_program_surface_flip_and_addr()
341 void hubp3_dcc_control(struct hubp *hubp, bool enable, in hubp3_dcc_control() argument
345 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp3_dcc_control()
354 void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp, in hubp3_dcc_control_sienna_cichlid() argument
357 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp3_dcc_control_sienna_cichlid()
369 struct hubp *hubp, in hubp3_dmdata_set_attributes() argument
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Ddcn30_hubp.h256 void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
260 struct hubp *hubp,
265 struct hubp *hubp,
275 struct hubp *hubp,
281 void hubp3_dcc_control(struct hubp *hubp, bool enable,
284 void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,
288 struct hubp *hubp,
291 void hubp3_read_state(struct hubp *hubp);
293 void hubp3_init(struct hubp *hubp);
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_hubp.c42 void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow) in hubp32_update_force_pstate_disallow() argument
44 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp32_update_force_pstate_disallow()
50 void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor) in hubp32_update_mall_sel() argument
52 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp32_update_mall_sel()
59 void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable) in hubp32_prepare_subvp_buffering() argument
61 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp32_prepare_subvp_buffering()
77 void hubp32_phantom_hubp_post_enable(struct hubp *hubp) in hubp32_phantom_hubp_post_enable() argument
80 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp32_phantom_hubp_post_enable()
100 struct hubp *hubp, in hubp32_cursor_set_attributes() argument
103 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp32_cursor_set_attributes()
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Ddcn32_hubp.h53 void hubp32_update_force_pstate_disallow(struct hubp *hubp, bool pstate_disallow);
55 void hubp32_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
57 void hubp32_prepare_subvp_buffering(struct hubp *hubp, bool enable);
59 void hubp32_phantom_hubp_post_enable(struct hubp *hubp);
61 void hubp32_cursor_set_attributes(struct hubp *hubp,
Ddcn32_hwseq.c279 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_calculate_cab_allocation() local
281 if (pipe->stream && pipe->plane_state && hubp) in dcn32_calculate_cab_allocation()
285 if (hubp->curs_attr.width > 0) { in dcn32_calculate_cab_allocation()
286 cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; in dcn32_calculate_cab_allocation()
520 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mpc_shaper_3dlut()
556 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mcm_luts()
645 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_output_transfer_func()
685 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_subvp_update_force_pstate() local
687 if (hubp && hubp->funcs->hubp_update_force_pstate_disallow) in dcn32_subvp_update_force_pstate()
688 hubp->funcs->hubp_update_force_pstate_disallow(hubp, false); in dcn32_subvp_update_force_pstate()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_hubp.c42 void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable) in hubp31_set_unbounded_requesting() argument
44 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp31_set_unbounded_requesting()
50 void hubp31_soft_reset(struct hubp *hubp, bool reset) in hubp31_soft_reset() argument
52 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp31_soft_reset()
57 static void hubp31_program_extended_blank(struct hubp *hubp, in hubp31_program_extended_blank() argument
60 struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); in hubp31_program_extended_blank()
Ddcn31_hubp.h242 void hubp31_soft_reset(struct hubp *hubp, bool reset);
244 void hubp31_set_unbounded_requesting(struct hubp *hubp, bool enable);
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubp.c78 struct hubp *hubp, in apply_DEDCN21_142_wa_for_hostvm_deadline() argument
81 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); in apply_DEDCN21_142_wa_for_hostvm_deadline()
128 struct hubp *hubp, in hubp21_program_deadline() argument
132 hubp2_program_deadline(hubp, dlg_attr, ttu_attr); in hubp21_program_deadline()
134 apply_DEDCN21_142_wa_for_hostvm_deadline(hubp, dlg_attr); in hubp21_program_deadline()
138 struct hubp *hubp, in hubp21_program_requestor() argument
141 struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp); in hubp21_program_requestor()
170 struct hubp *hubp, in hubp21_setup() argument
180 hubp2_vready_at_or_After_vsync(hubp, pipe_dest); in hubp21_setup()
181 hubp21_program_requestor(hubp, rq_regs); in hubp21_setup()
[all …]
Ddcn21_hubp.h32 #define TO_DCN21_HUBP(hubp)\ argument
33 container_of(hubp, struct dcn21_hubp, base)
106 struct hubp base;
123 struct hubp *hubp,
127 struct hubp *hubp,
132 struct hubp *hubp,
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/
Ddc_dmub_srv.c904 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dc_build_cursor_update_payload0() local
907 if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, in dc_build_cursor_update_payload0()
914 payload->cursor_rect.x = hubp->cur_rect.x; in dc_build_cursor_update_payload0()
915 payload->cursor_rect.y = hubp->cur_rect.y; in dc_build_cursor_update_payload0()
917 payload->cursor_rect.width = hubp->cur_rect.w; in dc_build_cursor_update_payload0()
918 payload->cursor_rect.height = hubp->cur_rect.h; in dc_build_cursor_update_payload0()
920 payload->enable = hubp->pos.cur_ctl.bits.cur_enable; in dc_build_cursor_update_payload0()
936 const struct hubp *hubp, const struct dpp *dpp) in dc_build_cursor_position_update_payload0() argument
939 pl->position_cfg.pHubp.cur_ctl.raw = hubp->pos.cur_ctl.raw; in dc_build_cursor_position_update_payload0()
940 pl->position_cfg.pHubp.position.raw = hubp->pos.position.raw; in dc_build_cursor_position_update_payload0()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/core/
Ddc_stream.c375 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in program_cursor_position()
670 struct hubp *hubp; in dc_stream_set_dynamic_metadata() local
690 hubp = pipe_ctx->plane_res.hubp; in dc_stream_set_dynamic_metadata()
691 if (hubp == NULL) in dc_stream_set_dynamic_metadata()
698 if (hubp->funcs->dmdata_set_attributes != NULL && in dc_stream_set_dynamic_metadata()
700 hubp->funcs->dmdata_set_attributes(hubp, attr); in dc_stream_set_dynamic_metadata()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/
Dhw_sequencer_private.h65 struct hubp;
114 struct hubp *hubp);
Dcore_types.h250 struct hubp *hubps[MAX_PIPES];
358 struct hubp *hubp; member

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