/linux-6.1.9/arch/arm64/boot/dts/arm/ |
D | rtsm_ve-aemv8a.dts | 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 22 interrupt-parent = <&gic>; 97 gic: interrupt-controller@2c001000 { label 98 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 138 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 139 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 140 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 141 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 142 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 143 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, [all …]
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D | fvp-base-revc.dts | 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 23 interrupt-parent = <&gic>; 115 gic: interrupt-controller@2f000000 { label 116 compatible = "arm,gic-v3"; 131 compatible = "arm,gic-v3-its"; 164 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 165 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 166 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 167 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 200 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, [all …]
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D | foundation-v8.dtsi | 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 17 interrupt-parent = <&gic>; 130 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 131 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 132 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 133 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 134 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 135 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 136 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 137 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, [all …]
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D | vexpress-v2m-rs1.dtsi | 20 #include <dt-bindings/interrupt-controller/arm-gic.h> 111 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 112 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 113 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 114 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 115 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 116 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 117 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 118 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 119 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, [all …]
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/linux-6.1.9/drivers/irqchip/ |
D | irq-gic.c | 339 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local 340 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq() 372 generic_handle_domain_irq(gic->domain, irqnr); in gic_handle_irq() 402 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); in gic_irq_print_chip() local 404 if (gic->domain->dev) in gic_irq_print_chip() 405 seq_printf(p, gic->domain->dev->of_node->name); in gic_irq_print_chip() 407 seq_printf(p, "GIC-%d", (int)(gic - &gic_data[0])); in gic_irq_print_chip() 417 static u8 gic_get_cpumask(struct gic_chip_data *gic) in gic_get_cpumask() argument 419 void __iomem *base = gic_data_dist_base(gic); in gic_get_cpumask() 442 static void gic_cpu_if_up(struct gic_chip_data *gic) in gic_cpu_if_up() argument [all …]
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D | irq-gic-pm.c | 28 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_resume() local 42 if (!gic) in gic_runtime_resume() 45 gic_dist_restore(gic); in gic_runtime_resume() 46 gic_cpu_restore(gic); in gic_runtime_resume() 54 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_suspend() local 57 gic_dist_save(gic); in gic_runtime_suspend() 58 gic_cpu_save(gic); in gic_runtime_suspend()
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D | Makefile | 30 obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o 31 obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o 32 obj-$(CONFIG_ARCH_REALVIEW) += irq-gic-realview.o 33 obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o 34 obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o 35 obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o 36 obj-$(CONFIG_ARM_GIC_V3_ITS_PCI) += irq-gic-v3-its-pci-msi.o 37 obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o 71 obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o
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/linux-6.1.9/arch/arm/boot/dts/ |
D | bcm5301x.dtsi | 15 #include <dt-bindings/interrupt-controller/arm-gic.h> 20 interrupt-parent = <&gic>; 88 gic: interrupt-controller@21000 { label 89 compatible = "arm,cortex-a9-gic"; 162 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 165 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 166 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 167 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 168 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 169 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, [all …]
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D | vexpress-v2m-rs1.dtsi | 20 #include <dt-bindings/interrupt-controller/arm-gic.h> 111 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 112 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 113 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 114 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 115 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 116 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 117 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 118 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 119 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, [all …]
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D | vexpress-v2m.dtsi | 20 #include <dt-bindings/interrupt-controller/arm-gic.h> 32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 40 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, [all …]
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D | bcm53573.dtsi | 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 interrupt-parent = <&gic>; 41 gic: interrupt-controller@1000 { label 42 compatible = "arm,cortex-a7-gic"; 82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, [all …]
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D | exynos54xx.dtsi | 30 interrupt-parent = <&gic>; 84 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 85 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 86 <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 87 <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 88 <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 89 <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 90 <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 91 <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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/linux-6.1.9/Documentation/devicetree/bindings/interrupt-controller/ |
D | arm,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml# 29 - arm,arm11mp-gic 30 - arm,cortex-a15-gic 31 - arm,cortex-a7-gic 32 - arm,cortex-a5-gic 33 - arm,cortex-a9-gic 34 - arm,eb11mp-gic 35 - arm,gic-400 37 - arm,tc11mp-gic 42 - const: arm,gic-400 [all …]
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D | renesas,rza1-irqc.yaml | 63 #include <dt-bindings/interrupt-controller/arm-gic.h> 71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 76 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 77 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 78 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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D | mti,gic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml# 21 const: mti,gic 27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the 73 const: mti,gic-timer 107 #include <dt-bindings/interrupt-controller/mips-gic.h> 111 compatible = "mti,gic"; 119 compatible = "mti,gic-timer"; 125 #include <dt-bindings/interrupt-controller/mips-gic.h> 129 compatible = "mti,gic"; 135 compatible = "mti,gic-timer"; [all …]
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D | fsl,ls-extirq.yaml | 103 #include <dt-bindings/interrupt-controller/arm-gic.h> 111 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 112 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 113 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 114 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 115 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 116 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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/linux-6.1.9/arch/arm64/boot/dts/xilinx/ |
D | zynqmp.dtsi | 105 interrupt-parent = <&gic>; 133 interrupt-parent = <&gic>; 153 interrupt-parent = <&gic>; 191 interrupt-parent = <&gic>; 218 interrupt-parent = <&gic>; 230 interrupt-parent = <&gic>; 247 interrupt-parent = <&gic>; 261 interrupt-parent = <&gic>; 274 interrupt-parent = <&gic>; 287 interrupt-parent = <&gic>; [all …]
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/linux-6.1.9/arch/arm64/boot/dts/cavium/ |
D | thunder2-99xx.dtsi | 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 15 interrupt-parent = <&gic>; 58 gic: interrupt-controller@400080000 { label 59 compatible = "arm,gic-v3"; 70 gicits: gic-its@40010000 { 71 compatible = "arm,gic-v3-its"; 121 <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 122 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 123 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH 124 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; [all …]
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/linux-6.1.9/Documentation/devicetree/bindings/bus/ |
D | brcm,bus-axi.txt | 34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
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/linux-6.1.9/arch/arm64/boot/dts/freescale/ |
D | s32v234.dtsi | 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 interrupt-parent = <&gic>; 87 gic: interrupt-controller@7d001000 { label 88 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 104 interrupt-parent = <&gic>; 111 interrupt-parent = <&gic>; 127 interrupt-parent = <&gic>;
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/linux-6.1.9/arch/arm64/boot/dts/renesas/ |
D | r9a07g054l1.dtsi | 20 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 21 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 22 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 23 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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D | r9a07g044l1.dtsi | 20 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 21 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 22 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 23 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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D | r9a07g044c1.dtsi | 20 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 21 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 22 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 23 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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/linux-6.1.9/arch/mips/boot/dts/ralink/ |
D | mt7621.dtsi | 2 #include <dt-bindings/interrupt-controller/mips-gic.h> 86 interrupt-parent = <&gic>; 119 interrupt-parent = <&gic>; 255 interrupt-parent = <&gic>; 268 interrupt-parent = <&gic>; 272 gic: interrupt-controller@1fbc0000 { label 273 compatible = "mti,gic"; 282 compatible = "mti,gic-timer"; 312 interrupt-parent = <&gic>; 423 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, [all …]
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/linux-6.1.9/Documentation/devicetree/bindings/pci/ |
D | hisilicon,kirin-pcie.yaml | 67 #include <dt-bindings/interrupt-controller/arm-gic.h> 94 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 95 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 96 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 97 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 126 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 127 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 128 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 129 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
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