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Searched refs:gam_regs (Results 1 – 8 of 8) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_cm.c97 struct color_matrices_reg gam_regs; in program_gamut_remap() local
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
125 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in program_gamut_remap()
126 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); in program_gamut_remap()
131 &gam_regs); in program_gamut_remap()
135 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); in program_gamut_remap()
136 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); in program_gamut_remap()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dwb_cm.c85 struct dcn3_xfer_func_reg gam_regs; in dwb3_program_ogam_luta_settings() local
87 dwb3_get_reg_field_ogam(dwbc30, &gam_regs); in dwb3_program_ogam_luta_settings()
89 gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B); in dwb3_program_ogam_luta_settings()
90 gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G); in dwb3_program_ogam_luta_settings()
91 gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R); in dwb3_program_ogam_luta_settings()
92 gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B); in dwb3_program_ogam_luta_settings()
93 gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G); in dwb3_program_ogam_luta_settings()
94 gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R); in dwb3_program_ogam_luta_settings()
95 gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B); in dwb3_program_ogam_luta_settings()
96 gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G); in dwb3_program_ogam_luta_settings()
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Ddcn30_dpp_cm.c224 struct dcn3_xfer_func_reg gam_regs; in dpp3_program_gamcor_lut() local
247 gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B); in dpp3_program_gamcor_lut()
248 gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G); in dpp3_program_gamcor_lut()
249 gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R); in dpp3_program_gamcor_lut()
250 gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B); in dpp3_program_gamcor_lut()
251 gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G); in dpp3_program_gamcor_lut()
252 gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R); in dpp3_program_gamcor_lut()
253 gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B); in dpp3_program_gamcor_lut()
254 gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B); in dpp3_program_gamcor_lut()
255 gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMB_END_CNTL1_G); in dpp3_program_gamcor_lut()
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Ddcn30_mpc.c211 struct dcn3_xfer_func_reg gam_regs; in mpc3_program_luta() local
213 mpc3_ogam_get_reg_field(mpc, &gam_regs); in mpc3_program_luta()
215 gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]); in mpc3_program_luta()
216 gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]); in mpc3_program_luta()
217 gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]); in mpc3_program_luta()
218 gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_B[mpcc_id]); in mpc3_program_luta()
219 gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_G[mpcc_id]); in mpc3_program_luta()
220 gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_START_SLOPE_CNTL_R[mpcc_id]); in mpc3_program_luta()
221 gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]); in mpc3_program_luta()
222 gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]); in mpc3_program_luta()
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Ddcn30_dpp.c66 struct color_matrices_reg gam_regs; in dpp3_program_post_csc() local
100 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; in dpp3_program_post_csc()
101 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11; in dpp3_program_post_csc()
102 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12; in dpp3_program_post_csc()
103 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12; in dpp3_program_post_csc()
107 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_C11_C12); in dpp3_program_post_csc()
108 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_C33_C34); in dpp3_program_post_csc()
112 gam_regs.csc_c11_c12 = REG(CM_POST_CSC_B_C11_C12); in dpp3_program_post_csc()
113 gam_regs.csc_c33_c34 = REG(CM_POST_CSC_B_C33_C34); in dpp3_program_post_csc()
120 &gam_regs); in dpp3_program_post_csc()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mpc.c326 struct xfer_func_reg gam_regs; in mpc2_program_lutb() local
328 mpc2_ogam_get_reg_field(mpc, &gam_regs); in mpc2_program_lutb()
330 gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]); in mpc2_program_lutb()
331 gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]); in mpc2_program_lutb()
332 gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]); in mpc2_program_lutb()
333 gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_B[mpcc_id]); in mpc2_program_lutb()
334 gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_G[mpcc_id]); in mpc2_program_lutb()
335 gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]); in mpc2_program_lutb()
336 gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]); in mpc2_program_lutb()
337 gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]); in mpc2_program_lutb()
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Ddcn20_dpp_cm.c167 struct color_matrices_reg gam_regs; in program_gamut_remap() local
189 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
191 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
192 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
195 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); in program_gamut_remap()
196 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); in program_gamut_remap()
198 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_B_C11_C12); in program_gamut_remap()
199 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_B_C33_C34); in program_gamut_remap()
205 &gam_regs); in program_gamut_remap()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_mpc.c172 struct dcn3_xfer_func_reg gam_regs; in mpc32_program_post1dluta_settings() local
174 mpc32_post1dlut_get_reg_field(mpc30, &gam_regs); in mpc32_program_post1dluta_settings()
176 gam_regs.start_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_B[mpcc_id]); in mpc32_program_post1dluta_settings()
177 gam_regs.start_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_G[mpcc_id]); in mpc32_program_post1dluta_settings()
178 gam_regs.start_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_CNTL_R[mpcc_id]); in mpc32_program_post1dluta_settings()
179 gam_regs.start_slope_cntl_b = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B[mpcc_id]); in mpc32_program_post1dluta_settings()
180 gam_regs.start_slope_cntl_g = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G[mpcc_id]); in mpc32_program_post1dluta_settings()
181 gam_regs.start_slope_cntl_r = REG(MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R[mpcc_id]); in mpc32_program_post1dluta_settings()
182 gam_regs.start_end_cntl1_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL1_B[mpcc_id]); in mpc32_program_post1dluta_settings()
183 gam_regs.start_end_cntl2_b = REG(MPCC_MCM_1DLUT_RAMA_END_CNTL2_B[mpcc_id]); in mpc32_program_post1dluta_settings()
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