| /linux-6.1.9/drivers/gpu/drm/mediatek/ |
| D | mtk_drm_ddp_comp.h | 80 const struct mtk_ddp_comp_funcs *funcs; member
85 if (comp->funcs && comp->funcs->clk_enable) in mtk_ddp_comp_clk_enable()
86 return comp->funcs->clk_enable(comp->dev); in mtk_ddp_comp_clk_enable()
93 if (comp->funcs && comp->funcs->clk_disable) in mtk_ddp_comp_clk_disable()
94 comp->funcs->clk_disable(comp->dev); in mtk_ddp_comp_clk_disable()
102 if (comp->funcs && comp->funcs->config) in mtk_ddp_comp_config()
103 comp->funcs->config(comp->dev, w, h, vrefresh, bpc, cmdq_pkt); in mtk_ddp_comp_config()
108 if (comp->funcs && comp->funcs->start) in mtk_ddp_comp_start()
109 comp->funcs->start(comp->dev); in mtk_ddp_comp_start()
114 if (comp->funcs && comp->funcs->stop) in mtk_ddp_comp_stop()
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| /linux-6.1.9/drivers/gpu/drm/ |
| D | drm_simple_kms_helper.c | 92 if (!pipe->funcs || !pipe->funcs->mode_valid) in drm_simple_kms_crtc_mode_valid()
96 return pipe->funcs->mode_valid(pipe, mode); in drm_simple_kms_crtc_mode_valid()
119 if (!pipe->funcs || !pipe->funcs->enable) in drm_simple_kms_crtc_enable()
123 pipe->funcs->enable(pipe, crtc->state, plane->state); in drm_simple_kms_crtc_enable()
132 if (!pipe->funcs || !pipe->funcs->disable) in drm_simple_kms_crtc_disable()
135 pipe->funcs->disable(pipe); in drm_simple_kms_crtc_disable()
150 if (!pipe->funcs || !pipe->funcs->reset_crtc) in drm_simple_kms_crtc_reset()
153 return pipe->funcs->reset_crtc(pipe); in drm_simple_kms_crtc_reset()
161 if (!pipe->funcs || !pipe->funcs->duplicate_crtc_state) in drm_simple_kms_crtc_duplicate_state()
164 return pipe->funcs->duplicate_crtc_state(pipe); in drm_simple_kms_crtc_duplicate_state()
[all …]
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| D | drm_bridge.c | 218 state = bridge->funcs->atomic_duplicate_state(bridge); in drm_bridge_atomic_duplicate_priv_state()
229 bridge->funcs->atomic_destroy_state(bridge, state); in drm_bridge_atomic_destroy_priv_state()
283 if (bridge->funcs->attach) { in drm_bridge_attach()
284 ret = bridge->funcs->attach(bridge, flags); in drm_bridge_attach()
289 if (bridge->funcs->atomic_reset) { in drm_bridge_attach()
292 state = bridge->funcs->atomic_reset(bridge); in drm_bridge_attach()
306 if (bridge->funcs->detach) in drm_bridge_attach()
307 bridge->funcs->detach(bridge); in drm_bridge_attach()
334 if (bridge->funcs->atomic_reset) in drm_bridge_detach()
337 if (bridge->funcs->detach) in drm_bridge_detach()
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| D | drm_panel.c | 58 const struct drm_panel_funcs *funcs, int connector_type) in drm_panel_init() argument
62 panel->funcs = funcs; in drm_panel_init()
111 if (panel->funcs && panel->funcs->prepare) in drm_panel_prepare()
112 return panel->funcs->prepare(panel); in drm_panel_prepare()
134 if (panel->funcs && panel->funcs->unprepare) in drm_panel_unprepare()
135 return panel->funcs->unprepare(panel); in drm_panel_unprepare()
158 if (panel->funcs && panel->funcs->enable) { in drm_panel_enable()
159 ret = panel->funcs->enable(panel); in drm_panel_enable()
195 if (panel->funcs && panel->funcs->disable) in drm_panel_disable()
196 return panel->funcs->disable(panel); in drm_panel_disable()
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| D | drm_atomic_helper.c | 120 const struct drm_connector_helper_funcs *funcs = connector->helper_private; in handle_conflicting_encoders() local
126 if (funcs->atomic_best_encoder) in handle_conflicting_encoders()
127 new_encoder = funcs->atomic_best_encoder(connector, in handle_conflicting_encoders()
129 else if (funcs->best_encoder) in handle_conflicting_encoders()
130 new_encoder = funcs->best_encoder(connector); in handle_conflicting_encoders()
295 const struct drm_connector_helper_funcs *funcs; in update_connector_routing() local
351 funcs = connector->helper_private; in update_connector_routing()
353 if (funcs->atomic_best_encoder) in update_connector_routing()
354 new_encoder = funcs->atomic_best_encoder(connector, state); in update_connector_routing()
355 else if (funcs->best_encoder) in update_connector_routing()
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| D | drm_encoder.c | 77 if (encoder->funcs && encoder->funcs->late_register) in drm_encoder_register_all()
78 ret = encoder->funcs->late_register(encoder); in drm_encoder_register_all()
91 if (encoder->funcs && encoder->funcs->early_unregister) in drm_encoder_unregister_all()
92 encoder->funcs->early_unregister(encoder); in drm_encoder_unregister_all()
99 const struct drm_encoder_funcs *funcs, in __drm_encoder_init() argument
114 encoder->funcs = funcs; in __drm_encoder_init()
161 const struct drm_encoder_funcs *funcs, in drm_encoder_init() argument
167 WARN_ON(!funcs->destroy); in drm_encoder_init()
170 ret = __drm_encoder_init(dev, encoder, funcs, encoder_type, name, ap); in drm_encoder_init()
219 const struct drm_encoder_funcs *funcs, in __drmm_encoder_init() argument
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| D | drm_client.c | 80 const char *name, const struct drm_client_funcs *funcs) in drm_client_init() argument
87 if (funcs && !try_module_get(funcs->owner)) in drm_client_init()
92 client->funcs = funcs; in drm_client_init()
109 if (funcs) in drm_client_init()
110 module_put(funcs->owner); in drm_client_init()
159 if (client->funcs) in drm_client_release()
160 module_put(client->funcs->owner); in drm_client_release()
174 if (client->funcs && client->funcs->unregister) { in drm_client_dev_unregister()
175 client->funcs->unregister(client); in drm_client_dev_unregister()
203 if (!client->funcs || !client->funcs->hotplug) in drm_client_dev_hotplug()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_srv.c | 153 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; in dmub_srv_hw_setup() local
164 funcs->reset = dmub_dcn20_reset; in dmub_srv_hw_setup()
165 funcs->reset_release = dmub_dcn20_reset_release; in dmub_srv_hw_setup()
166 funcs->backdoor_load = dmub_dcn20_backdoor_load; in dmub_srv_hw_setup()
167 funcs->setup_windows = dmub_dcn20_setup_windows; in dmub_srv_hw_setup()
168 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; in dmub_srv_hw_setup()
169 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; in dmub_srv_hw_setup()
170 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; in dmub_srv_hw_setup()
171 funcs->is_supported = dmub_dcn20_is_supported; in dmub_srv_hw_setup()
172 funcs->is_hw_init = dmub_dcn20_is_hw_init; in dmub_srv_hw_setup()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hwseq.c | 93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
96 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd… in enable_memory_low_power()
99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); in enable_memory_low_power()
102 …dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->… in enable_memory_low_power()
117 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) in dcn31_init_hw()
118 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); in dcn31_init_hw()
136 if (hws->funcs.enable_power_gating_plane) in dcn31_init_hw()
137 hws->funcs.enable_power_gating_plane(hws, true); in dcn31_init_hw()
142 if (!dcb->funcs->is_accelerated_mode(dcb)) { in dcn31_init_hw()
143 hws->funcs.bios_golden_init(dc); in dcn31_init_hw()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 114 !tg->funcs->is_tg_enabled(tg)) in dcn10_lock_all_pipes()
146 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
179 hubp->funcs->hubp_read_state(hubp); in dcn10_log_hubp_states()
301 dpp->funcs->dpp_read_state(dpp, &s); in dcn10_log_hw_state()
342 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s); in dcn10_log_hw_state()
366 if (pool->opps[i]->funcs->dpg_is_blanked) in dcn10_log_hw_state()
367 s.blank_enabled = pool->opps[i]->funcs->dpg_is_blanked(pool->opps[i]); in dcn10_log_hw_state()
369 s.blank_enabled = tg->funcs->is_blanked(tg); in dcn10_log_hw_state()
400 tg->funcs->clear_optc_underflow(tg); in dcn10_log_hw_state()
411 dsc->funcs->dsc_read_state(dsc, &s); in dcn10_log_hw_state()
[all …]
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| /linux-6.1.9/lib/ |
| D | test_min_heap.c | 34 const struct min_heap_callbacks *funcs) in pop_verify_heap() argument
41 min_heap_pop(heap, funcs); in pop_verify_heap()
57 min_heap_pop(heap, funcs); in pop_verify_heap()
71 struct min_heap_callbacks funcs = { in test_heapify_all() local
79 min_heapify_all(&heap, &funcs); in test_heapify_all()
80 err = pop_verify_heap(min_heap, &heap, &funcs); in test_heapify_all()
88 min_heapify_all(&heap, &funcs); in test_heapify_all()
89 err += pop_verify_heap(min_heap, &heap, &funcs); in test_heapify_all()
104 struct min_heap_callbacks funcs = { in test_heap_push() local
113 min_heap_push(&heap, &data[i], &funcs); in test_heap_push()
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| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ib.c | 169 (!ring->funcs->secure_submission_supported)) { in amdgpu_ib_schedule()
174 alloc_size = ring->funcs->emit_frame_size + num_ibs * in amdgpu_ib_schedule()
175 ring->funcs->emit_ib_size; in amdgpu_ib_schedule()
184 if (ring->funcs->emit_pipeline_sync && job && in amdgpu_ib_schedule()
196 if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) in amdgpu_ib_schedule()
197 ring->funcs->emit_mem_sync(ring); in amdgpu_ib_schedule()
199 if (ring->funcs->emit_wave_limit && in amdgpu_ib_schedule()
201 ring->funcs->emit_wave_limit(ring, true); in amdgpu_ib_schedule()
203 if (ring->funcs->insert_start) in amdgpu_ib_schedule()
204 ring->funcs->insert_start(ring); in amdgpu_ib_schedule()
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| D | amdgpu_psp.h | 311 const struct psp_funcs *funcs; member
392 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
393 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
394 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
395 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
397 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
399 ((psp)->funcs->bootloader_load_kdb ? (psp)->funcs->bootloader_load_kdb((psp)) : 0)
401 ((psp)->funcs->bootloader_load_spl ? (psp)->funcs->bootloader_load_spl((psp)) : 0)
403 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
405 ((psp)->funcs->bootloader_load_soc_drv ? (psp)->funcs->bootloader_load_soc_drv((psp)) : 0)
[all …]
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| D | amdgpu_display.h | 26 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((…
27 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level…
28 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e…
29 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
30 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), …
31 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
32 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
33 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev)…
34 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page…
35 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e),…
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| D | amdgpu_ring.c | 65 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; in amdgpu_ring_alloc()
76 if (ring->funcs->begin_use) in amdgpu_ring_alloc()
77 ring->funcs->begin_use(ring); in amdgpu_ring_alloc()
94 amdgpu_ring_write(ring, ring->funcs->nop); in amdgpu_ring_insert_nop()
107 while (ib->length_dw & ring->funcs->align_mask) in amdgpu_ring_generic_pad_ib()
108 ib->ptr[ib->length_dw++] = ring->funcs->nop; in amdgpu_ring_generic_pad_ib()
125 count = ring->funcs->align_mask + 1 - in amdgpu_ring_commit()
126 (ring->wptr & ring->funcs->align_mask); in amdgpu_ring_commit()
127 count %= ring->funcs->align_mask + 1; in amdgpu_ring_commit()
128 ring->funcs->insert_nop(ring, count); in amdgpu_ring_commit()
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| D | sienna_cichlid.c | 85 r = adev->ip_blocks[i].version->funcs->suspend(adev); in sienna_cichlid_mode2_suspend_ip()
90 adev->ip_blocks[i].version->funcs->name, r); in sienna_cichlid_mode2_suspend_ip()
107 if (adev->gfxhub.funcs->mode2_save_regs) in sienna_cichlid_mode2_prepare_hwcontext()
108 adev->gfxhub.funcs->mode2_save_regs(adev); in sienna_cichlid_mode2_prepare_hwcontext()
109 if (adev->gfxhub.funcs->halt) in sienna_cichlid_mode2_prepare_hwcontext()
110 adev->gfxhub.funcs->halt(adev); in sienna_cichlid_mode2_prepare_hwcontext()
168 if (adev->gfxhub.funcs->mode2_restore_regs) in sienna_cichlid_mode2_restore_ip()
169 adev->gfxhub.funcs->mode2_restore_regs(adev); in sienna_cichlid_mode2_restore_ip()
170 adev->gfxhub.funcs->init(adev); in sienna_cichlid_mode2_restore_ip()
171 r = adev->gfxhub.funcs->gart_enable(adev); in sienna_cichlid_mode2_restore_ip()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.c | 167 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && in dcn20_setup_gsl_group_as_lock()
168 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { in dcn20_setup_gsl_group_as_lock()
169 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
173 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
183 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) in dcn20_set_flip_control_gsl()
184 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( in dcn20_set_flip_control_gsl()
270 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_triple_buffer()
271 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( in dcn20_program_triple_buffer()
295 tg->funcs->get_otg_active_size(tg, in dcn20_init_blank()
300 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn20_init_blank()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_hw_sequencer.c | 229 bp_result = dcb->funcs->enable_disp_power_gating( in dce110_enable_display_power_gating()
298 ipp->funcs->ipp_program_prescale(ipp, &prescale_params); in dce110_set_input_transfer_func()
303 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); in dce110_set_input_transfer_func()
307 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); in dce110_set_input_transfer_func()
311 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); in dce110_set_input_transfer_func()
314 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); in dce110_set_input_transfer_func()
317 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); in dce110_set_input_transfer_func()
325 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); in dce110_set_input_transfer_func()
616 xfm->funcs->opp_power_on_regamma_lut(xfm, true); in dce110_set_output_transfer_func()
622 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); in dce110_set_output_transfer_func()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.c | 89 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn30_set_blend_lut()
129 acquired_rmu = mpc->funcs->acquire_rmu(mpc, mpcc_id, in dcn30_set_mpc_shaper_3dlut()
133 result = mpc->funcs->program_3dlut(mpc, in dcn30_set_mpc_shaper_3dlut()
136 result = mpc->funcs->program_shaper(mpc, shaper_lut, in dcn30_set_mpc_shaper_3dlut()
140 mpc->funcs->release_rmu(mpc, mpcc_id); in dcn30_set_mpc_shaper_3dlut()
165 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn30_set_input_transfer_func()
176 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); in dcn30_set_input_transfer_func()
179 if (dpp_base->funcs->dpp_program_blnd_lut) in dcn30_set_input_transfer_func()
180 hws->funcs.set_blend_lut(pipe_ctx, plane_state); in dcn30_set_input_transfer_func()
181 if (dpp_base->funcs->dpp_program_shaper_lut && in dcn30_set_input_transfer_func()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_hwseq.c | 146 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( in dcn201_update_plane_addr()
177 tg->funcs->get_otg_active_size(tg, in dcn201_init_blank()
182 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn201_init_blank()
186 opp->funcs->opp_set_disp_pattern_generator( in dcn201_init_blank()
196 hws->funcs.wait_for_blank_complete(opp); in dcn201_init_blank()
228 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
229 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
231 if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks) in dcn201_init_hw()
232 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); in dcn201_init_hw()
238 hws->funcs.dccg_init(hws); in dcn201_init_hw()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/link/ |
| D | link_hwss_dio.c | 35 stream_encoder->funcs->set_throttled_vcp_size( in set_dio_throttled_vcp_size()
45 link_enc->funcs->connect_dig_be_to_fe(link_enc, in setup_dio_stream_encoder()
50 if (stream_enc->funcs->enable_fifo) in setup_dio_stream_encoder()
51 stream_enc->funcs->enable_fifo(stream_enc); in setup_dio_stream_encoder()
59 if (stream_enc && stream_enc->funcs->disable_fifo) in reset_dio_stream_encoder()
60 stream_enc->funcs->disable_fifo(stream_enc); in reset_dio_stream_encoder()
62 link_enc->funcs->connect_dig_be_to_fe( in reset_dio_stream_encoder()
79 stream_encoder->funcs->setup_stereo_sync( in setup_dio_stream_attribute()
85 stream_encoder->funcs->dp_set_stream_attribute( in setup_dio_stream_attribute()
92 stream_encoder->funcs->hdmi_set_stream_attribute( in setup_dio_stream_attribute()
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| D | link_hwss_hpo_dp.c | 58 hpo_dp_link_encoder->funcs->set_throttled_vcp_size(hpo_dp_link_encoder, in set_hpo_dp_throttled_vcp_size()
86 hpo_dp_stream_encoder->funcs->set_hblank_min_symbol_width(hpo_dp_stream_encoder, in set_hpo_dp_hblank_min_symbol_width()
117 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); in setup_hpo_dp_stream_encoder()
119 dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, stream_enc->inst); in setup_hpo_dp_stream_encoder()
120 dccg->funcs->enable_symclk32_se(dccg, stream_enc->inst, phyd32clk); in setup_hpo_dp_stream_encoder()
121 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); in setup_hpo_dp_stream_encoder()
122 stream_enc->funcs->enable_stream(stream_enc); in setup_hpo_dp_stream_encoder()
123 stream_enc->funcs->map_stream_to_link(stream_enc, stream_enc->inst, link_enc->inst); in setup_hpo_dp_stream_encoder()
137 stream_enc->funcs->disable(stream_enc); in reset_hpo_dp_stream_encoder()
138 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); in reset_hpo_dp_stream_encoder()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_hwseq.c | 503 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); in dcn32_subvp_pipe_control_lock()
540 result = mpc->funcs->program_3dlut(mpc, in dcn32_set_mpc_shaper_3dlut()
544 result = mpc->funcs->program_shaper(mpc, in dcn32_set_mpc_shaper_3dlut()
572 result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); in dcn32_set_mcm_luts()
588 result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); in dcn32_set_mcm_luts()
592 result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func->lut_3d, mpcc_id); in dcn32_set_mcm_luts()
594 result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); in dcn32_set_mcm_luts()
620 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn32_set_input_transfer_func()
631 dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); in dcn32_set_input_transfer_func()
635 hws->funcs.set_mcm_luts) in dcn32_set_input_transfer_func()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/ |
| D | dc_edid_parser.c | 38 dmcu->funcs->is_dmcu_initialized(dmcu) && in dc_edid_parser_send_cea()
39 dmcu->funcs->send_edid_cea) { in dc_edid_parser_send_cea()
40 return dmcu->funcs->send_edid_cea(dmcu, in dc_edid_parser_send_cea()
55 dmcu->funcs->is_dmcu_initialized(dmcu) && in dc_edid_parser_recv_cea_ack()
56 dmcu->funcs->recv_edid_cea_ack) { in dc_edid_parser_recv_cea_ack()
57 return dmcu->funcs->recv_edid_cea_ack(dmcu, offset); in dc_edid_parser_recv_cea_ack()
71 dmcu->funcs->is_dmcu_initialized(dmcu) && in dc_edid_parser_recv_amd_vsdb()
72 dmcu->funcs->recv_amd_vsdb) { in dc_edid_parser_recv_amd_vsdb()
73 return dmcu->funcs->recv_amd_vsdb(dmcu, in dc_edid_parser_recv_amd_vsdb()
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| /linux-6.1.9/drivers/gpu/drm/msm/ |
| D | msm_atomic.c | 77 kms->funcs->enable_commit(kms); in msm_atomic_async_commit()
85 kms->funcs->flush_commit(kms, crtc_mask); in msm_atomic_async_commit()
91 kms->funcs->wait_flush(kms, crtc_mask); in msm_atomic_async_commit()
96 kms->funcs->complete_commit(kms, crtc_mask); in msm_atomic_async_commit()
98 kms->funcs->disable_commit(kms); in msm_atomic_async_commit()
189 bool async = kms->funcs->vsync_time && in msm_atomic_commit_tail()
194 kms->funcs->enable_commit(kms); in msm_atomic_commit_tail()
202 kms->funcs->wait_flush(kms, crtc_mask); in msm_atomic_commit_tail()
209 kms->funcs->prepare_commit(kms, state); in msm_atomic_commit_tail()
234 vsync_time = kms->funcs->vsync_time(kms, async_crtc); in msm_atomic_commit_tail()
[all …]
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