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Searched refs:feature_mask (Results 1 – 25 of 53) sorted by relevance

123

/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/
Dsmu_cmn.c581 uint64_t *feature_mask) in smu_cmn_get_enabled_mask() argument
587 if (!feature_mask) in smu_cmn_get_enabled_mask()
590 feature_mask_low = &((uint32_t *)feature_mask)[0]; in smu_cmn_get_enabled_mask()
591 feature_mask_high = &((uint32_t *)feature_mask)[1]; in smu_cmn_get_enabled_mask()
637 uint64_t feature_mask, in smu_cmn_feature_update_enable_state() argument
645 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
651 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
656 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
662 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
704 uint64_t feature_mask; in smu_cmn_get_pp_feature_mask() local
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Dsmu_cmn.h64 uint64_t *feature_mask);
71 uint64_t feature_mask,
Dsmu_internal.h75 …e smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0,… argument
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dhwmgr.c102 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
113 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
118 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
123 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
131 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; in hwmgr_early_init()
136 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
144 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
149 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
160 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
170 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
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Dvega20_hwmgr.c104 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK)) in vega20_set_default_registry_data()
107 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK)) in vega20_set_default_registry_data()
110 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK)) in vega20_set_default_registry_data()
113 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK)) in vega20_set_default_registry_data()
116 if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK)) in vega20_set_default_registry_data()
119 if (!(hwmgr->feature_mask & PP_ULV_MASK)) in vega20_set_default_registry_data()
122 if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)) in vega20_set_default_registry_data()
174 data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); in vega20_set_default_registry_data()
1816 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) in vega20_upload_dpm_min_level() argument
1824 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { in vega20_upload_dpm_min_level()
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Dvega10_hwmgr.c121 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
123 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
125 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
127 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; in vega10_set_default_registry_data()
130 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
132 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { in vega10_set_default_registry_data()
139 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; in vega10_set_default_registry_data()
142 hwmgr->feature_mask & PP_ULV_MASK ? true : false; in vega10_set_default_registry_data()
145 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; in vega10_set_default_registry_data()
154 hwmgr->feature_mask & PP_AVFS_MASK ? true : false; in vega10_set_default_registry_data()
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/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dsmu_v13_0_7_ppt.c247 uint32_t *feature_mask, uint32_t num) in smu_v13_0_7_get_allowed_feature_mask() argument
254 memset(feature_mask, 0, sizeof(uint32_t) * num); in smu_v13_0_7_get_allowed_feature_mask()
256 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); in smu_v13_0_7_get_allowed_feature_mask()
259 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
260 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); in smu_v13_0_7_get_allowed_feature_mask()
261 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); in smu_v13_0_7_get_allowed_feature_mask()
265 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in smu_v13_0_7_get_allowed_feature_mask()
268 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
269 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); in smu_v13_0_7_get_allowed_feature_mask()
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Dsmu_v13_0_0_ppt.c269 uint32_t *feature_mask, uint32_t num) in smu_v13_0_0_get_allowed_feature_mask() argument
277 memset(feature_mask, 0xff, sizeof(uint32_t) * num); in smu_v13_0_0_get_allowed_feature_mask()
280 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask()
281 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); in smu_v13_0_0_get_allowed_feature_mask()
286 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); in smu_v13_0_0_get_allowed_feature_mask()
289 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask()
295 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); in smu_v13_0_0_get_allowed_feature_mask()
298 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); in smu_v13_0_0_get_allowed_feature_mask()
299 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); in smu_v13_0_0_get_allowed_feature_mask()
300 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); in smu_v13_0_0_get_allowed_feature_mask()
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Daldebaran_ppt.c296 uint32_t *feature_mask, uint32_t num) in aldebaran_get_allowed_feature_mask() argument
302 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); in aldebaran_get_allowed_feature_mask()
935 uint32_t feature_mask, in aldebaran_upload_dpm_level() argument
944 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { in aldebaran_upload_dpm_level()
958 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { in aldebaran_upload_dpm_level()
972 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { in aldebaran_upload_dpm_level()
1672 uint32_t feature_mask; member
1698 if (throttler_status & logging_label[throttler_idx].feature_mask) { in aldebaran_log_thermal_throttling_event()
/linux-6.1.9/drivers/thermal/intel/int340x_thermal/
Dprocessor_thermal_device.c401 kernel_ulong_t feature_mask) in proc_thermal_mmio_add() argument
405 proc_priv->mmio_feature_mask = feature_mask; in proc_thermal_mmio_add()
407 if (feature_mask) { in proc_thermal_mmio_add()
413 if (feature_mask & PROC_THERMAL_FEATURE_RAPL) { in proc_thermal_mmio_add()
421 if (feature_mask & PROC_THERMAL_FEATURE_FIVR || in proc_thermal_mmio_add()
422 feature_mask & PROC_THERMAL_FEATURE_DVFS) { in proc_thermal_mmio_add()
430 if (feature_mask & PROC_THERMAL_FEATURE_MBOX) { in proc_thermal_mmio_add()
Dprocessor_thermal_device.h93 kernel_ulong_t feature_mask);
/linux-6.1.9/arch/arm64/kernel/
Dalternative.c144 unsigned long *feature_mask) in __apply_alternatives() argument
154 if (!test_bit(cap, feature_mask)) in __apply_alternatives()
193 feature_mask, ARM64_NCAPS); in __apply_alternatives()
/linux-6.1.9/drivers/mfd/
Dkempld-core.c67 pld->feature_mask = kempld_read16(pld, KEMPLD_FEATURE); in kempld_get_info_generic()
69 pld->feature_mask = 0; in kempld_get_info_generic()
97 if (pld->feature_mask & KEMPLD_FEATURE_BIT_I2C) in kempld_register_cells_generic()
100 if (pld->feature_mask & KEMPLD_FEATURE_BIT_WATCHDOG) in kempld_register_cells_generic()
103 if (pld->feature_mask & KEMPLD_FEATURE_BIT_GPIO) in kempld_register_cells_generic()
106 if (pld->feature_mask & KEMPLD_FEATURE_MASK_UART) in kempld_register_cells_generic()
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dvega10_smumgr.h46 bool enable, uint32_t feature_mask);
Dvega12_smumgr.h52 bool enable, uint64_t feature_mask);
Dvega20_smumgr.h51 bool enable, uint64_t feature_mask);
Dvega12_smumgr.c126 bool enable, uint64_t feature_mask) in vega12_enable_smc_features() argument
130 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega12_enable_smc_features()
131 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega12_enable_smc_features()
Dvega20_smumgr.c318 bool enable, uint64_t feature_mask) in vega20_enable_smc_features() argument
323 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); in vega20_enable_smc_features()
324 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); in vega20_enable_smc_features()
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dcyan_skillfish_ppt.c556 uint64_t *feature_mask) in cyan_skillfish_get_enabled_mask() argument
558 if (!feature_mask) in cyan_skillfish_get_enabled_mask()
560 memset(feature_mask, 0xff, sizeof(*feature_mask)); in cyan_skillfish_get_enabled_mask()
Dnavi10_ppt.c279 uint32_t *feature_mask, uint32_t num) in navi10_get_allowed_feature_mask() argument
286 memset(feature_mask, 0, sizeof(uint32_t) * num); in navi10_get_allowed_feature_mask()
288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) in navi10_get_allowed_feature_mask()
310 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in navi10_get_allowed_feature_mask()
313 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); in navi10_get_allowed_feature_mask()
316 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); in navi10_get_allowed_feature_mask()
319 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); in navi10_get_allowed_feature_mask()
322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); in navi10_get_allowed_feature_mask()
325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in navi10_get_allowed_feature_mask()
328 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); in navi10_get_allowed_feature_mask()
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/linux-6.1.9/include/sound/sof/
Dext_manifest4.h74 uint32_t feature_mask; member
/linux-6.1.9/drivers/net/
Dtap.c941 netdev_features_t feature_mask = 0; in set_offload() local
950 feature_mask = NETIF_F_HW_CSUM; in set_offload()
954 feature_mask |= NETIF_F_TSO_ECN; in set_offload()
956 feature_mask |= NETIF_F_TSO; in set_offload()
958 feature_mask |= NETIF_F_TSO6; in set_offload()
970 if (feature_mask & (NETIF_F_TSO | NETIF_F_TSO6)) in set_offload()
978 tap->tap_features = feature_mask; in set_offload()
/linux-6.1.9/arch/x86/mm/
Dmem_encrypt_identity.c509 unsigned long feature_mask; in sme_enable() local
547 feature_mask = (sev_status & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT; in sme_enable()
554 if (feature_mask == AMD_SME_BIT) { in sme_enable()
/linux-6.1.9/include/linux/mfd/
Dkempld.h91 u32 feature_mask; member
/linux-6.1.9/sound/soc/intel/avs/
Dtopology.h70 u32 feature_mask; member

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