| /linux-6.1.9/drivers/clk/zynqmp/ |
| D | pll.c | 104 u32 fbdiv; in zynqmp_pll_round_rate() local
117 fbdiv = DIV_ROUND_CLOSEST(rate, *prate); in zynqmp_pll_round_rate()
118 if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) { in zynqmp_pll_round_rate()
119 fbdiv = clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); in zynqmp_pll_round_rate()
120 rate = *prate * fbdiv; in zynqmp_pll_round_rate()
139 u32 fbdiv, data; in zynqmp_pll_recalc_rate() local
145 ret = zynqmp_pm_clock_getdivider(clk_id, &fbdiv); in zynqmp_pll_recalc_rate()
156 rate = parent_rate * fbdiv; in zynqmp_pll_recalc_rate()
183 u32 fbdiv; in zynqmp_pll_set_rate() local
209 fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate); in zynqmp_pll_set_rate()
[all …]
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| /linux-6.1.9/drivers/clk/zynq/ |
| D | pll.c | 54 u32 fbdiv; in zynq_pll_round_rate() local
56 fbdiv = DIV_ROUND_CLOSEST(rate, *prate); in zynq_pll_round_rate()
57 if (fbdiv < PLL_FBDIV_MIN) in zynq_pll_round_rate()
58 fbdiv = PLL_FBDIV_MIN; in zynq_pll_round_rate()
59 else if (fbdiv > PLL_FBDIV_MAX) in zynq_pll_round_rate()
60 fbdiv = PLL_FBDIV_MAX; in zynq_pll_round_rate()
62 return *prate * fbdiv; in zynq_pll_round_rate()
75 u32 fbdiv; in zynq_pll_recalc_rate() local
81 fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
84 return parent_rate * fbdiv; in zynq_pll_recalc_rate()
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| /linux-6.1.9/drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 231 u8 fbdiv, divq, best_r, r; in wrpll_configure_for_rate() local
267 fbdiv = __wrpll_calc_fbdiv(c); in wrpll_configure_for_rate()
279 f >>= (fbdiv - 1); in wrpll_configure_for_rate()
282 vco_pre = fbdiv * post_divr_freq; in wrpll_configure_for_rate()
337 u8 fbdiv; in wrpll_calc_output_rate() local
345 fbdiv = __wrpll_calc_fbdiv(c); in wrpll_calc_output_rate()
346 n = parent_rate * fbdiv * (c->divf + 1); in wrpll_calc_output_rate()
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| /linux-6.1.9/drivers/clk/pistachio/ |
| D | clk-pll.c | 211 vco *= (params->fbdiv << 24) + params->frac; in pll_gf40lp_frac_set_rate()
230 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT); in pll_gf40lp_frac_set_rate()
273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
277 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; in pll_gf40lp_frac_recalc_rate()
289 rate *= (fbdiv << 24) + frac; in pll_gf40lp_frac_recalc_rate()
291 rate *= (fbdiv << 24); in pll_gf40lp_frac_recalc_rate()
366 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
398 (params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) | in pll_gf40lp_laint_set_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
418 fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK; in pll_gf40lp_laint_recalc_rate()
[all …]
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| D | clk.h | 98 unsigned long long fbdiv; member
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| /linux-6.1.9/drivers/clk/axs10x/ |
| D | i2s_pll_clock.c | 27 unsigned int fbdiv; member
102 unsigned int idiv, fbdiv, odiv; in i2s_pll_recalc_rate() local
105 fbdiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_FBDIV_REG)); in i2s_pll_recalc_rate()
108 return ((parent_rate / idiv) * fbdiv) / odiv; in i2s_pll_recalc_rate()
145 i2s_pll_write(clk, PLL_FBDIV_REG, pll_cfg[i].fbdiv); in i2s_pll_set_rate()
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| D | pll_clock.c | 70 u32 fbdiv; member
140 u32 idiv, fbdiv, odiv; in axs10x_pll_recalc_rate() local
144 fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV)); in axs10x_pll_recalc_rate()
147 rate = (u64)parent_rate * fbdiv; in axs10x_pll_recalc_rate()
186 axs10x_encode_div(pll_cfg[i].fbdiv, 0)); in axs10x_pll_set_rate()
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| /linux-6.1.9/drivers/clk/mmp/ |
| D | clk-pll.c | 49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
59 fbdiv = (val >> pll->shift) & 0x1ff; in mmp_clk_pll_recalc_rate()
62 fbdiv = 2; in mmp_clk_pll_recalc_rate()
74 rate *= 2 * fbdiv; in mmp_clk_pll_recalc_rate()
88 rate *= fbdiv + 2; in mmp_clk_pll_recalc_rate()
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| /linux-6.1.9/drivers/clk/rockchip/ |
| D | clk-pll.c | 145 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) in rockchip_rk3036_pll_get_params()
172 rate64 *= cur.fbdiv; in rockchip_rk3036_pll_recalc_rate()
201 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
214 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
318 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
321 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
324 if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || in rockchip_rk3036_pll_init()
625 rate->fbdiv = ((pllcon >> RK3399_PLLCON0_FBDIV_SHIFT) in rockchip_rk3399_pll_get_params()
654 rate64 *= cur.fbdiv; in rockchip_rk3399_pll_recalc_rate()
683 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3399_pll_set_params()
[all …]
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| D | clk.h | 249 .fbdiv = _fbdiv, \
303 unsigned int fbdiv; member
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| /linux-6.1.9/drivers/clk/berlin/ |
| D | berlin2-pll.c | 46 u32 val, fbdiv, rfdiv, vcodivsel, vcodiv; in berlin2_pll_recalc_rate() local
50 fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK; in berlin2_pll_recalc_rate()
66 rate *= fbdiv * map->mult; in berlin2_pll_recalc_rate()
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| D | berlin2-avpll.c | 159 u32 reg, refdiv, fbdiv; in berlin2_avpll_vco_recalc_rate() local
166 fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT; in berlin2_avpll_vco_recalc_rate()
167 freq *= fbdiv; in berlin2_avpll_vco_recalc_rate()
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| /linux-6.1.9/drivers/clk/ |
| D | clk-hsdk-pll.c | 50 u32 fbdiv; member
143 val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; in hsdk_pll_set_cfg()
173 u32 idiv, fbdiv, odiv; in hsdk_pll_recalc_rate() local
191 fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT)); in hsdk_pll_recalc_rate()
195 rate = (u64)parent_rate * fbdiv; in hsdk_pll_recalc_rate()
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| D | clk-axm5516.c | 52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
57 fbdiv = ((control >> 4) & 0xfff) + 3; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
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| D | clk-bm1880.c | 477 u32 fbdiv, refdiv; in bm1880_pll_rate_calc() local
480 fbdiv = (regval >> 16) & 0xfff; in bm1880_pll_rate_calc()
485 numerator = parent_rate * fbdiv; in bm1880_pll_rate_calc()
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| /linux-6.1.9/drivers/phy/rockchip/ |
| D | phy-rockchip-inno-hdmi.c | 254 u16 fbdiv; member
269 u16 fbdiv; member
642 RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3228_clk_set_rate()
645 inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_clk_set_rate()
800 inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val); in inno_hdmi_phy_rk3328_clk_set_rate()
801 inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3328_clk_set_rate()
914 RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
915 inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3228_power_on()
1022 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); in inno_hdmi_phy_rk3328_power_on()
1025 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | in inno_hdmi_phy_rk3328_power_on()
[all …]
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| D | phy-rockchip-inno-dsidphy.c | 221 u16 fbdiv; member
364 inno->pll.fbdiv = best_fbdiv; in inno_dsidphy_pll_calc_rate()
392 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); in inno_dsidphy_mipi_mode_enable()
394 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); in inno_dsidphy_mipi_mode_enable()
535 u16 fbdiv = 28; in inno_dsidphy_lvds_mode_enable() local
550 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv)); in inno_dsidphy_lvds_mode_enable()
552 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); in inno_dsidphy_lvds_mode_enable()
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| /linux-6.1.9/drivers/gpu/drm/radeon/ |
| D | rv740_dpm.c | 132 u32 fbdiv; in rv740_populate_sclk_value() local
144 fbdiv = (u32) tmp; in rv740_populate_sclk_value()
154 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); in rv740_populate_sclk_value()
164 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); in rv740_populate_sclk_value()
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| D | rv730_dpm.c | 51 u32 fbdiv; in rv730_populate_sclk_value() local
69 fbdiv = (u32) tmp; in rv730_populate_sclk_value()
85 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); in rv730_populate_sclk_value()
95 u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); in rv730_populate_sclk_value()
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| D | rs780_dpm.c | 212 u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in rs780_preset_starting_fbdiv() local
214 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
217 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
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| /linux-6.1.9/sound/soc/codecs/ |
| D | madera.c | 4423 int refdiv, fref, fout, lockdet_thr, fbdiv, hp, fast_clk, fllgcd; in madera_fllhj_apply() local
4447 fbdiv = 256; in madera_fllhj_apply()
4449 fbdiv = 4; in madera_fllhj_apply()
4453 fbdiv = 1; in madera_fllhj_apply()
4457 fbdiv = 1; in madera_fllhj_apply()
4482 while (ratio / fbdiv < min_n) { in madera_fllhj_apply()
4483 fbdiv /= 2; in madera_fllhj_apply()
4484 if (fbdiv < 1) { in madera_fllhj_apply()
4485 madera_fll_err(fll, "FBDIV (%d) must be >= 1\n", fbdiv); in madera_fllhj_apply()
4489 while (frac && (ratio / fbdiv > max_n)) { in madera_fllhj_apply()
[all …]
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| /linux-6.1.9/drivers/clk/ralink/ |
| D | clk-mt7621.c | 256 u32 pll, prediv, fbdiv; in mt7621_cpu_recalc_rate() local
272 fbdiv = FIELD_GET(CPU_PLL_FBDIV_MASK, pll); in mt7621_cpu_recalc_rate()
274 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; in mt7621_cpu_recalc_rate()
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| /linux-6.1.9/drivers/clk/xilinx/ |
| D | xlnx_vcu.c | 90 u32 fbdiv; member
279 if (xvcu_pll_cfg[i].fbdiv == div) in xvcu_find_cfg()
298 vcu_pll_ctrl |= FIELD_PREP(VCU_PLL_CTRL_FBDIV, cfg->fbdiv); in xvcu_pll_set_div()
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| /linux-6.1.9/arch/arm/common/ |
| D | sa1111.c | 1181 unsigned int skcdr, fbdiv, ipdiv, opdiv; in __sa1111_pll_clock() local
1185 fbdiv = (skcdr & 0x007f) + 2; in __sa1111_pll_clock()
1189 return 3686400 * fbdiv / (ipdiv * opdiv); in __sa1111_pll_clock()
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| /linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | fiji_smumgr.c | 867 uint32_t fbdiv; in fiji_calculate_sclk_params() local
882 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in fiji_calculate_sclk_params()
892 SPLL_FB_DIV, fbdiv); in fiji_calculate_sclk_params()
915 fbdiv / (clk_s * 10000); in fiji_calculate_sclk_params()
|