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Searched refs:f32_cntl (Results 1 – 7 of 7) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dsdma_v3_0.c556 u32 f32_cntl, phase_quantum = 0; in sdma_v3_0_ctx_switch_enable() local
584 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in sdma_v3_0_ctx_switch_enable()
586 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
588 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
597 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
599 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
603 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_ctx_switch_enable()
617 u32 f32_cntl; in sdma_v3_0_enable() local
626 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v3_0_enable()
628 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v3_0_enable()
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Dsdma_v2_4.c382 u32 f32_cntl; in sdma_v2_4_enable() local
391 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
393 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_enable()
395 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v2_4_enable()
396 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable()
Dsdma_v5_2.c454 u32 f32_cntl, phase_quantum = 0; in sdma_v5_2_ctx_switch_enable() local
492 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_2_ctx_switch_enable()
493 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_2_ctx_switch_enable()
495 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_2_ctx_switch_enable()
511 u32 f32_cntl; in sdma_v5_2_enable() local
521 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_enable()
522 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_2_enable()
523 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_2_enable()
Dcik_sdma.c347 u32 f32_cntl, phase_quantum = 0; in cik_ctx_switch_enable() local
375 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in cik_ctx_switch_enable()
377 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in cik_ctx_switch_enable()
386 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in cik_ctx_switch_enable()
390 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in cik_ctx_switch_enable()
Dsdma_v5_0.c624 u32 f32_cntl = 0, phase_quantum = 0; in sdma_v5_0_ctx_switch_enable() local
653 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_0_ctx_switch_enable()
654 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_0_ctx_switch_enable()
667 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_0_ctx_switch_enable()
682 u32 f32_cntl; in sdma_v5_0_enable() local
694 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_enable()
695 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v5_0_enable()
696 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_0_enable()
Dsdma_v4_0.c981 u32 f32_cntl, phase_quantum = 0; in sdma_v4_0_ctx_switch_enable() local
1009 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); in sdma_v4_0_ctx_switch_enable()
1010 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v4_0_ctx_switch_enable()
1017 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); in sdma_v4_0_ctx_switch_enable()
1043 u32 f32_cntl; in sdma_v4_0_enable() local
1054 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); in sdma_v4_0_enable()
1055 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v4_0_enable()
1056 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); in sdma_v4_0_enable()
Dsdma_v6_0.c450 u32 f32_cntl; in sdma_v6_0_enable() local
459 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); in sdma_v6_0_enable()
460 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); in sdma_v6_0_enable()
461 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl); in sdma_v6_0_enable()