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Searched refs:eq (Results 1 – 25 of 213) sorted by relevance

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/linux-6.1.9/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_eqs.c27 #define GET_EQ_NUM_PAGES(eq, pg_size) \ argument
28 (ALIGN((eq)->q_len * (eq)->elem_size, pg_size) / (pg_size))
30 #define GET_EQ_NUM_ELEMS_IN_PG(eq, pg_size) ((pg_size) / (eq)->elem_size) argument
32 #define EQ_CONS_IDX_REG_ADDR(eq) (((eq)->type == HINIC_AEQ) ? \ argument
33 HINIC_CSR_AEQ_CONS_IDX_ADDR((eq)->q_id) : \
34 HINIC_CSR_CEQ_CONS_IDX_ADDR((eq)->q_id))
36 #define EQ_PROD_IDX_REG_ADDR(eq) (((eq)->type == HINIC_AEQ) ? \ argument
37 HINIC_CSR_AEQ_PROD_IDX_ADDR((eq)->q_id) : \
38 HINIC_CSR_CEQ_PROD_IDX_ADDR((eq)->q_id))
40 #define EQ_HI_PHYS_ADDR_REG(eq, pg_num) (((eq)->type == HINIC_AEQ) ? \ argument
[all …]
/linux-6.1.9/drivers/infiniband/hw/erdma/
Derdma_eq.c11 void notify_eq(struct erdma_eq *eq) in notify_eq() argument
13 u64 db_data = FIELD_PREP(ERDMA_EQDB_CI_MASK, eq->ci) | in notify_eq()
16 *eq->db_record = db_data; in notify_eq()
17 writeq(db_data, eq->db_addr); in notify_eq()
19 atomic64_inc(&eq->notify_num); in notify_eq()
22 void *get_next_valid_eqe(struct erdma_eq *eq) in get_next_valid_eqe() argument
24 u64 *eqe = get_queue_entry(eq->qbuf, eq->ci, eq->depth, EQE_SHIFT); in get_next_valid_eqe()
27 return owner ^ !!(eq->ci & eq->depth) ? eqe : NULL; in get_next_valid_eqe()
85 struct erdma_eq *eq = &dev->aeq; in erdma_aeq_init() local
88 eq->depth = ERDMA_DEFAULT_EQ_DEPTH; in erdma_aeq_init()
[all …]
Derdma_cmdq.c154 struct erdma_eq *eq = &cmdq->eq; in erdma_cmdq_eq_init() local
157 eq->depth = cmdq->max_outstandings; in erdma_cmdq_eq_init()
158 buf_size = eq->depth << EQE_SHIFT; in erdma_cmdq_eq_init()
160 eq->qbuf = in erdma_cmdq_eq_init()
162 &eq->qbuf_dma_addr, GFP_KERNEL | __GFP_ZERO); in erdma_cmdq_eq_init()
163 if (!eq->qbuf) in erdma_cmdq_eq_init()
166 spin_lock_init(&eq->lock); in erdma_cmdq_eq_init()
167 atomic64_set(&eq->event_num, 0); in erdma_cmdq_eq_init()
169 eq->db_addr = in erdma_cmdq_eq_init()
171 eq->db_record = (u64 *)(eq->qbuf + buf_size); in erdma_cmdq_eq_init()
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/linux-6.1.9/drivers/net/ethernet/mellanox/mlx5/core/
Deq.c91 static struct mlx5_core_cq *mlx5_eq_cq_get(struct mlx5_eq *eq, u32 cqn) in mlx5_eq_cq_get() argument
93 struct mlx5_cq_table *table = &eq->cq_table; in mlx5_eq_cq_get()
111 struct mlx5_eq *eq = &eq_comp->core; in mlx5_eq_comp_int() local
116 eqe = next_eqe_sw(eq); in mlx5_eq_comp_int()
130 cq = mlx5_eq_cq_get(eq, cqn); in mlx5_eq_comp_int()
136 dev_dbg_ratelimited(eq->dev->device, in mlx5_eq_comp_int()
140 ++eq->cons_index; in mlx5_eq_comp_int()
142 } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq))); in mlx5_eq_comp_int()
145 eq_update_ci(eq, 1); in mlx5_eq_comp_int()
158 u32 mlx5_eq_poll_irq_disabled(struct mlx5_eq_comp *eq) in mlx5_eq_poll_irq_disabled() argument
[all …]
Dcq.c95 struct mlx5_eq_comp *eq; in mlx5_create_cq() local
98 eq = mlx5_eqn2comp_eq(dev, eqn); in mlx5_create_cq()
99 if (IS_ERR(eq)) in mlx5_create_cq()
100 return PTR_ERR(eq); in mlx5_create_cq()
111 cq->eq = eq; in mlx5_create_cq()
118 cq->tasklet_ctx.priv = &eq->tasklet_ctx; in mlx5_create_cq()
122 err = mlx5_eq_add_cq(&eq->core, cq); in mlx5_create_cq()
138 cq->irqn = eq->core.irqn; in mlx5_create_cq()
143 mlx5_eq_del_cq(&eq->core, cq); in mlx5_create_cq()
171 mlx5_eq_del_cq(&cq->eq->core, cq); in mlx5_core_destroy_cq()
/linux-6.1.9/sound/pci/au88x0/
Dau88x0_eq.c56 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftCoefs()
78 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightCoefs()
101 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftStates()
118 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightStates()
164 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetBypassGain()
211 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftGainsTarget()
221 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightGainsTarget()
231 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetLeftGainsCurrent()
241 eqhw_t *eqhw = &(vortex->eq.this04); in vortex_EqHw_SetRightGainsCurrent()
252 eqhw_t *eqhw = &(vortex->eq.this04);
[all …]
/linux-6.1.9/drivers/infiniband/hw/mthca/
Dmthca_eq.c173 static inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in tavor_set_eq_ci() argument
184 mthca_write64(MTHCA_EQ_DB_SET_CI | eq->eqn, ci & (eq->nent - 1), in tavor_set_eq_ci()
189 static inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in arbel_set_eq_ci() argument
194 dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8); in arbel_set_eq_ci()
199 static inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) in set_eq_ci() argument
202 arbel_set_eq_ci(dev, eq, ci); in set_eq_ci()
204 tavor_set_eq_ci(dev, eq, ci); in set_eq_ci()
228 static inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry) in get_eqe() argument
230 unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE; in get_eqe()
231 return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE; in get_eqe()
[all …]
/linux-6.1.9/drivers/net/ethernet/mellanox/mlx4/
Deq.c97 static void eq_set_ci(struct mlx4_eq *eq, int req_not) in eq_set_ci() argument
99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | in eq_set_ci()
101 eq->doorbell); in eq_set_ci()
106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor, in get_eqe() argument
110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size; in get_eqe()
118 …return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % … in get_eqe()
121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size) in next_eqe_sw() argument
123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); in next_eqe_sw()
124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; in next_eqe_sw()
241 struct mlx4_eq *eq = &priv->eq_table.eq[vec]; in mlx4_set_eq_affinity_hint() local
[all …]
/linux-6.1.9/drivers/net/ethernet/mellanox/mlx5/core/lib/
Deq.h51 static inline u32 eq_get_size(struct mlx5_eq *eq) in eq_get_size() argument
53 return eq->fbc.sz_m1 + 1; in eq_get_size()
56 static inline struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) in get_eqe() argument
58 return mlx5_frag_buf_get_wqe(&eq->fbc, entry); in get_eqe()
61 static inline struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) in next_eqe_sw() argument
63 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & eq->fbc.sz_m1); in next_eqe_sw()
65 return (eqe->owner ^ (eq->cons_index >> eq->fbc.log_sz)) & 1 ? NULL : eqe; in next_eqe_sw()
68 static inline void eq_update_ci(struct mlx5_eq *eq, int arm) in eq_update_ci() argument
70 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); in eq_update_ci()
71 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); in eq_update_ci()
[all …]
/linux-6.1.9/drivers/scsi/elx/efct/
Defct_hw_queues.c14 struct hw_eq *eq = NULL; in efct_hw_init_queues() local
34 eq = efct_hw_new_eq(hw, EFCT_HW_EQ_DEPTH); in efct_hw_init_queues()
35 if (!eq) { in efct_hw_init_queues()
40 eqs[i] = eq; in efct_hw_init_queues()
44 cq = efct_hw_new_cq(eq, in efct_hw_init_queues()
59 cq = efct_hw_new_cq(eq, hw->num_qentries[SLI4_QTYPE_CQ]); in efct_hw_init_queues()
130 struct hw_eq *eq = kzalloc(sizeof(*eq), GFP_KERNEL); in efct_hw_new_eq() local
132 if (!eq) in efct_hw_new_eq()
135 eq->type = SLI4_QTYPE_EQ; in efct_hw_new_eq()
136 eq->hw = hw; in efct_hw_new_eq()
[all …]
/linux-6.1.9/arch/powerpc/kernel/
Dcpu_setup_6xx.S191 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
192 cror 4*cr0+eq,4*cr0+eq,4*cr2+eq
342 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
344 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
345 cror 4*cr0+eq,4*cr0+eq,4*cr4+eq
346 cror 4*cr0+eq,4*cr0+eq,4*cr1+eq
347 cror 4*cr0+eq,4*cr0+eq,4*cr5+eq
348 cror 4*cr0+eq,4*cr0+eq,4*cr7+eq
413 cror 4*cr1+eq,4*cr1+eq,4*cr2+eq
415 cror 4*cr0+eq,4*cr0+eq,4*cr3+eq
[all …]
/linux-6.1.9/drivers/pci/controller/
Dpcie-iproc-msi.c64 unsigned int eq; member
130 unsigned int eq) in iproc_msi_read_reg() argument
134 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
139 int eq, u32 val) in iproc_msi_write_reg() argument
143 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
160 static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq) in iproc_msi_eq_offset() argument
163 return eq * EQ_MEM_REGION_SIZE; in iproc_msi_eq_offset()
165 return eq * EQ_LEN * sizeof(u32); in iproc_msi_eq_offset()
303 static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head) in decode_msi_hwirq() argument
309 offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32); in decode_msi_hwirq()
[all …]
/linux-6.1.9/drivers/net/ethernet/ibm/ehea/
Dehea_qmr.c236 struct ehea_eq *eq; in ehea_create_eq() local
238 eq = kzalloc(sizeof(*eq), GFP_KERNEL); in ehea_create_eq()
239 if (!eq) in ehea_create_eq()
242 eq->adapter = adapter; in ehea_create_eq()
243 eq->attr.type = type; in ehea_create_eq()
244 eq->attr.max_nr_of_eqes = max_nr_of_eqes; in ehea_create_eq()
245 eq->attr.eqe_gen = eqe_gen; in ehea_create_eq()
246 spin_lock_init(&eq->spinlock); in ehea_create_eq()
249 &eq->attr, &eq->fw_handle); in ehea_create_eq()
255 ret = hw_queue_ctor(&eq->hw_queue, eq->attr.nr_pages, in ehea_create_eq()
[all …]
/linux-6.1.9/include/linux/mlx5/
Deq.h24 mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
25 int mlx5_eq_enable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
27 void mlx5_eq_disable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
30 struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc);
31 void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm);
41 static inline u32 mlx5_eq_update_cc(struct mlx5_eq *eq, u32 cc) in mlx5_eq_update_cc() argument
44 mlx5_eq_update_ci(eq, cc, 0); in mlx5_eq_update_cc()
/linux-6.1.9/drivers/net/ethernet/microsoft/mana/
Dgdma_main.c199 req.log2_throttle_limit = queue->eq.log2_throttle_limit; in mana_gd_create_hw_eq()
200 req.eq_pci_msix_index = queue->eq.msix_index; in mana_gd_create_hw_eq()
210 queue->eq.disable_needed = true; in mana_gd_create_hw_eq()
256 e.eq.id = qid; in mana_gd_ring_doorbell()
257 e.eq.tail_ptr = tail_ptr; in mana_gd_ring_doorbell()
258 e.eq.arm = num_req; in mana_gd_ring_doorbell()
315 static void mana_gd_process_eqe(struct gdma_queue *eq) in mana_gd_process_eqe() argument
317 u32 head = eq->head % (eq->queue_size / GDMA_EQE_SIZE); in mana_gd_process_eqe()
318 struct gdma_context *gc = eq->gdma_dev->gdma_context; in mana_gd_process_eqe()
319 struct gdma_eqe *eq_eqe_ptr = eq->queue_mem_ptr; in mana_gd_process_eqe()
[all …]
/linux-6.1.9/drivers/infiniband/hw/mlx5/
Dodp.c79 struct mlx5_ib_pf_eq *eq; member
1381 struct mlx5_ib_pf_eq *eq = pfault->eq; in mlx5_ib_eqe_pf_action() local
1383 mlx5_ib_pfault(eq->dev, pfault); in mlx5_ib_eqe_pf_action()
1384 mempool_free(pfault, eq->pool); in mlx5_ib_eqe_pf_action()
1387 static void mlx5_ib_eq_pf_process(struct mlx5_ib_pf_eq *eq) in mlx5_ib_eq_pf_process() argument
1394 while ((eqe = mlx5_eq_get_eqe(eq->core, cc))) { in mlx5_ib_eq_pf_process()
1395 pfault = mempool_alloc(eq->pool, GFP_ATOMIC); in mlx5_ib_eq_pf_process()
1397 schedule_work(&eq->work); in mlx5_ib_eq_pf_process()
1405 mlx5_ib_dbg(eq->dev, in mlx5_ib_eq_pf_process()
1425 mlx5_ib_dbg(eq->dev, in mlx5_ib_eq_pf_process()
[all …]
/linux-6.1.9/arch/hexagon/lib/
Dmemset.S29 p0 = cmp.eq(r2, #0)
59 p1 = cmp.eq(r2, #1)
72 p1 = cmp.eq(r2, #2)
85 p1 = cmp.eq(r2, #4)
98 p1 = cmp.eq(r3, #1)
114 p1 = cmp.eq(r2, #8)
125 p1 = cmp.eq(r2, #4)
136 p1 = cmp.eq(r2, #2)
180 p1 = cmp.eq(r2, #1)
196 p0 = cmp.eq(r2, #2)
[all …]
/linux-6.1.9/drivers/net/ethernet/mellanox/mlx5/core/en/
Dhealth.c107 int mlx5e_health_eq_diag_fmsg(struct mlx5_eq_comp *eq, struct devlink_fmsg *fmsg) in mlx5e_health_eq_diag_fmsg() argument
115 err = devlink_fmsg_u8_pair_put(fmsg, "eqn", eq->core.eqn); in mlx5e_health_eq_diag_fmsg()
119 err = devlink_fmsg_u32_pair_put(fmsg, "irqn", eq->core.irqn); in mlx5e_health_eq_diag_fmsg()
123 err = devlink_fmsg_u32_pair_put(fmsg, "vecidx", eq->core.vecidx); in mlx5e_health_eq_diag_fmsg()
127 err = devlink_fmsg_u32_pair_put(fmsg, "ci", eq->core.cons_index); in mlx5e_health_eq_diag_fmsg()
131 err = devlink_fmsg_u32_pair_put(fmsg, "size", eq_get_size(&eq->core)); in mlx5e_health_eq_diag_fmsg()
206 int mlx5e_health_channel_eq_recover(struct net_device *dev, struct mlx5_eq_comp *eq, in mlx5e_health_channel_eq_recover() argument
212 eq->core.eqn, eq->core.cons_index, eq->core.irqn); in mlx5e_health_channel_eq_recover()
214 eqe_count = mlx5_eq_poll_irq_disabled(eq); in mlx5e_health_channel_eq_recover()
219 eqe_count, eq->core.eqn); in mlx5e_health_channel_eq_recover()
/linux-6.1.9/drivers/clk/spear/
Dspear1340_clock.c265 {.xscale = 5, .yscale = 122, .eq = 0},
267 {.xscale = 10, .yscale = 204, .eq = 0},
269 {.xscale = 4, .yscale = 25, .eq = 0},
271 {.xscale = 4, .yscale = 21, .eq = 0},
273 {.xscale = 5, .yscale = 18, .eq = 0},
275 {.xscale = 2, .yscale = 6, .eq = 0},
277 {.xscale = 5, .yscale = 12, .eq = 0},
279 {.xscale = 2, .yscale = 4, .eq = 0},
281 {.xscale = 5, .yscale = 18, .eq = 1},
283 {.xscale = 1, .yscale = 3, .eq = 1},
[all …]
/linux-6.1.9/arch/ia64/lib/
Dstrlen.S104 cmp.eq p6,p0=r0,r0 // sets p6 to true for cmp.and
119 cmp.eq.and p6,p0=8,val1 // p6 = p6 and val1==8
120 cmp.eq.and p6,p0=8,val2 // p6 = p6 and mask==8
130 cmp.eq p8,p9=8,val1 // p6 = val1 had zero (disambiguate)
137 cmp.eq.and p7,p0=8,val1// val1==8?
174 cmp.eq p0,p6=r0,r0 // nullify first ld8 in loop
184 cmp.eq p6,p0=8,val1 // val1==8 ?
/linux-6.1.9/drivers/infiniband/hw/efa/
Defa_main.c105 struct efa_eq *eq = data; in efa_intr_msix_comp() local
106 struct efa_com_dev *edev = eq->eeq.edev; in efa_intr_msix_comp()
108 efa_com_eq_comp_intr_handler(edev, &eq->eeq); in efa_intr_msix_comp()
139 static void efa_setup_comp_irq(struct efa_dev *dev, struct efa_eq *eq, in efa_setup_comp_irq() argument
145 snprintf(eq->irq.name, EFA_IRQNAME_SIZE, "efa-comp%d@pci:%s", cpu, in efa_setup_comp_irq()
147 eq->irq.handler = efa_intr_msix_comp; in efa_setup_comp_irq()
148 eq->irq.data = eq; in efa_setup_comp_irq()
149 eq->irq.vector = vector; in efa_setup_comp_irq()
150 eq->irq.irqn = pci_irq_vector(dev->pdev, vector); in efa_setup_comp_irq()
151 cpumask_set_cpu(cpu, &eq->irq.affinity_hint_mask); in efa_setup_comp_irq()
[all …]
/linux-6.1.9/drivers/misc/habanalabs/common/
Dirq.c374 struct hl_eq *eq = arg; in hl_irq_handler_eq() local
375 struct hl_device *hdev = eq->hdev; in hl_irq_handler_eq()
383 eq_base = eq->kernel_address; in hl_irq_handler_eq()
386 cur_eqe = le32_to_cpu(eq_base[eq->ci].hdr.ctl); in hl_irq_handler_eq()
394 (((eq->prev_eqe_index + 1) & EQ_CTL_INDEX_MASK) in hl_irq_handler_eq()
398 eq_base[eq->ci].hdr.ctl, in hl_irq_handler_eq()
399 ((eq->prev_eqe_index + 1) & EQ_CTL_INDEX_MASK), in hl_irq_handler_eq()
404 eq->prev_eqe_index++; in hl_irq_handler_eq()
406 eq_entry = &eq_base[eq->ci]; in hl_irq_handler_eq()
435 eq->ci = hl_eq_inc_ptr(eq->ci); in hl_irq_handler_eq()
[all …]
/linux-6.1.9/arch/arm64/lib/
Dcrc32.S75 csel x3, x3, x4, eq
76 csel w0, w0, w8, eq
80 csel x3, x3, x4, eq
81 csel w0, w0, w8, eq
85 csel w3, w3, w4, eq
86 csel w0, w0, w8, eq
89 csel w0, w0, w8, eq
93 csel w0, w0, w8, eq
/linux-6.1.9/net/dns_resolver/
Ddns_key.c150 const char *eq; in dns_resolver_preparse() local
161 eq = memchr(opt, '=', opt_len); in dns_resolver_preparse()
162 if (eq) { in dns_resolver_preparse()
163 opt_nlen = eq - opt; in dns_resolver_preparse()
164 eq++; in dns_resolver_preparse()
165 memcpy(optval, eq, next_opt - eq); in dns_resolver_preparse()
166 optval[next_opt - eq] = '\0'; in dns_resolver_preparse()
/linux-6.1.9/drivers/firmware/broadcom/
Dbcm47xx_nvram.c169 char *var, *value, *end, *eq; in bcm47xx_nvram_getenv() local
185 eq = strchr(var, '='); in bcm47xx_nvram_getenv()
186 if (!eq) in bcm47xx_nvram_getenv()
188 value = eq + 1; in bcm47xx_nvram_getenv()
189 if (eq - var == strlen(name) && in bcm47xx_nvram_getenv()
190 strncmp(var, name, eq - var) == 0) in bcm47xx_nvram_getenv()

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