1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2017-2019 NXP */
3
4 #include <linux/bitops.h>
5
6 /* ENETC device IDs */
7 #define ENETC_DEV_ID_PF 0xe100
8 #define ENETC_DEV_ID_VF 0xef00
9 #define ENETC_DEV_ID_PTP 0xee02
10
11 /* ENETC register block BAR */
12 #define ENETC_BAR_REGS 0
13
14 /** SI regs, offset: 0h */
15 #define ENETC_SIMR 0
16 #define ENETC_SIMR_EN BIT(31)
17 #define ENETC_SIMR_RSSE BIT(0)
18 #define ENETC_SICTR0 0x18
19 #define ENETC_SICTR1 0x1c
20 #define ENETC_SIPCAPR0 0x20
21 #define ENETC_SIPCAPR0_QBV BIT(4)
22 #define ENETC_SIPCAPR0_PSFP BIT(9)
23 #define ENETC_SIPCAPR0_RSS BIT(8)
24 #define ENETC_SIPCAPR1 0x24
25 #define ENETC_SITGTGR 0x30
26 #define ENETC_SIRBGCR 0x38
27 /* cache attribute registers for transactions initiated by ENETC */
28 #define ENETC_SICAR0 0x40
29 #define ENETC_SICAR1 0x44
30 #define ENETC_SICAR2 0x48
31 /* rd snoop, no alloc
32 * wr snoop, no alloc, partial cache line update for BDs and full cache line
33 * update for data
34 */
35 #define ENETC_SICAR_RD_COHERENT 0x2b2b0000
36 #define ENETC_SICAR_WR_COHERENT 0x00006727
37 #define ENETC_SICAR_MSI 0x00300030 /* rd/wr device, no snoop, no alloc */
38
39 #define ENETC_SIPMAR0 0x80
40 #define ENETC_SIPMAR1 0x84
41
42 /* VF-PF Message passing */
43 #define ENETC_DEFAULT_MSG_SIZE 1024 /* and max size */
44 /* msg size encoding: default and max msg value of 1024B encoded as 0 */
enetc_vsi_set_msize(u32 size)45 static inline u32 enetc_vsi_set_msize(u32 size)
46 {
47 return size < ENETC_DEFAULT_MSG_SIZE ? size >> 5 : 0;
48 }
49
50 #define ENETC_PSIMSGRR 0x204
51 #define ENETC_PSIMSGRR_MR_MASK GENMASK(2, 1)
52 #define ENETC_PSIMSGRR_MR(n) BIT((n) + 1) /* n = VSI index */
53 #define ENETC_PSIVMSGRCVAR0(n) (0x210 + (n) * 0x8) /* n = VSI index */
54 #define ENETC_PSIVMSGRCVAR1(n) (0x214 + (n) * 0x8)
55
56 #define ENETC_VSIMSGSR 0x204 /* RO */
57 #define ENETC_VSIMSGSR_MB BIT(0)
58 #define ENETC_VSIMSGSR_MS BIT(1)
59 #define ENETC_VSIMSGSNDAR0 0x210
60 #define ENETC_VSIMSGSNDAR1 0x214
61
62 #define ENETC_SIMSGSR_SET_MC(val) ((val) << 16)
63 #define ENETC_SIMSGSR_GET_MC(val) ((val) >> 16)
64
65 /* SI statistics */
66 #define ENETC_SIROCT 0x300
67 #define ENETC_SIRFRM 0x308
68 #define ENETC_SIRUCA 0x310
69 #define ENETC_SIRMCA 0x318
70 #define ENETC_SITOCT 0x320
71 #define ENETC_SITFRM 0x328
72 #define ENETC_SITUCA 0x330
73 #define ENETC_SITMCA 0x338
74 #define ENETC_RBDCR(n) (0x8180 + (n) * 0x200)
75
76 /* Control BDR regs */
77 #define ENETC_SICBDRMR 0x800
78 #define ENETC_SICBDRSR 0x804 /* RO */
79 #define ENETC_SICBDRBAR0 0x810
80 #define ENETC_SICBDRBAR1 0x814
81 #define ENETC_SICBDRPIR 0x818
82 #define ENETC_SICBDRCIR 0x81c
83 #define ENETC_SICBDRLENR 0x820
84
85 #define ENETC_SICAPR0 0x900
86 #define ENETC_SICAPR1 0x904
87
88 #define ENETC_PSIIER 0xa00
89 #define ENETC_PSIIER_MR_MASK GENMASK(2, 1)
90 #define ENETC_PSIIDR 0xa08
91 #define ENETC_SITXIDR 0xa18
92 #define ENETC_SIRXIDR 0xa28
93 #define ENETC_SIMSIVR 0xa30
94
95 #define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4)
96 #define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4)
97
98 #define ENETC_SIUEFDCR 0xe28
99
100 #define ENETC_SIRFSCAPR 0x1200
101 #define ENETC_SIRFSCAPR_GET_NUM_RFS(val) ((val) & 0x7f)
102 #define ENETC_SIRSSCAPR 0x1600
103 #define ENETC_SIRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
104
105 /** SI BDR sub-blocks, n = 0..7 */
106 enum enetc_bdr_type {TX, RX};
107 #define ENETC_BDR_OFF(i) ((i) * 0x200)
108 #define ENETC_BDR(t, i, r) (0x8000 + (t) * 0x100 + ENETC_BDR_OFF(i) + (r))
109 /* RX BDR reg offsets */
110 #define ENETC_RBMR 0
111 #define ENETC_RBMR_BDS BIT(2)
112 #define ENETC_RBMR_CM BIT(4)
113 #define ENETC_RBMR_VTE BIT(5)
114 #define ENETC_RBMR_EN BIT(31)
115 #define ENETC_RBSR 0x4
116 #define ENETC_RBBSR 0x8
117 #define ENETC_RBCIR 0xc
118 #define ENETC_RBBAR0 0x10
119 #define ENETC_RBBAR1 0x14
120 #define ENETC_RBPIR 0x18
121 #define ENETC_RBLENR 0x20
122 #define ENETC_RBIER 0xa0
123 #define ENETC_RBIER_RXTIE BIT(0)
124 #define ENETC_RBIDR 0xa4
125 #define ENETC_RBICR0 0xa8
126 #define ENETC_RBICR0_ICEN BIT(31)
127 #define ENETC_RBICR0_ICPT_MASK 0x1ff
128 #define ENETC_RBICR0_SET_ICPT(n) ((n) & ENETC_RBICR0_ICPT_MASK)
129 #define ENETC_RBICR1 0xac
130
131 /* TX BDR reg offsets */
132 #define ENETC_TBMR 0
133 #define ENETC_TBSR_BUSY BIT(0)
134 #define ENETC_TBMR_VIH BIT(9)
135 #define ENETC_TBMR_PRIO_MASK GENMASK(2, 0)
136 #define ENETC_TBMR_SET_PRIO(val) ((val) & ENETC_TBMR_PRIO_MASK)
137 #define ENETC_TBMR_EN BIT(31)
138 #define ENETC_TBSR 0x4
139 #define ENETC_TBBAR0 0x10
140 #define ENETC_TBBAR1 0x14
141 #define ENETC_TBPIR 0x18
142 #define ENETC_TBCIR 0x1c
143 #define ENETC_TBCIR_IDX_MASK 0xffff
144 #define ENETC_TBLENR 0x20
145 #define ENETC_TBIER 0xa0
146 #define ENETC_TBIER_TXTIE BIT(0)
147 #define ENETC_TBIDR 0xa4
148 #define ENETC_TBICR0 0xa8
149 #define ENETC_TBICR0_ICEN BIT(31)
150 #define ENETC_TBICR0_ICPT_MASK 0xf
151 #define ENETC_TBICR0_SET_ICPT(n) ((ilog2(n) + 1) & ENETC_TBICR0_ICPT_MASK)
152 #define ENETC_TBICR1 0xac
153
154 #define ENETC_RTBLENR_LEN(n) ((n) & ~0x7)
155
156 /* Port regs, offset: 1_0000h */
157 #define ENETC_PORT_BASE 0x10000
158 #define ENETC_PMR 0x0000
159 #define ENETC_PMR_EN GENMASK(18, 16)
160 #define ENETC_PMR_PSPEED_MASK GENMASK(11, 8)
161 #define ENETC_PMR_PSPEED_10M 0
162 #define ENETC_PMR_PSPEED_100M BIT(8)
163 #define ENETC_PMR_PSPEED_1000M BIT(9)
164 #define ENETC_PMR_PSPEED_2500M BIT(10)
165 #define ENETC_PSR 0x0004 /* RO */
166 #define ENETC_PSIPMR 0x0018
167 #define ENETC_PSIPMR_SET_UP(n) BIT(n) /* n = SI index */
168 #define ENETC_PSIPMR_SET_MP(n) BIT((n) + 16)
169 #define ENETC_PSIPVMR 0x001c
170 #define ENETC_VLAN_PROMISC_MAP_ALL 0x7
171 #define ENETC_PSIPVMR_SET_VP(simap) ((simap) & 0x7)
172 #define ENETC_PSIPVMR_SET_VUTA(simap) (((simap) & 0x7) << 16)
173 #define ENETC_PSIPMAR0(n) (0x0100 + (n) * 0x8) /* n = SI index */
174 #define ENETC_PSIPMAR1(n) (0x0104 + (n) * 0x8)
175 #define ENETC_PVCLCTR 0x0208
176 #define ENETC_PCVLANR1 0x0210
177 #define ENETC_PCVLANR2 0x0214
178 #define ENETC_VLAN_TYPE_C BIT(0)
179 #define ENETC_VLAN_TYPE_S BIT(1)
180 #define ENETC_PVCLCTR_OVTPIDL(bmp) ((bmp) & 0xff) /* VLAN_TYPE */
181 #define ENETC_PSIVLANR(n) (0x0240 + (n) * 4) /* n = SI index */
182 #define ENETC_PSIVLAN_EN BIT(31)
183 #define ENETC_PSIVLAN_SET_QOS(val) ((u32)(val) << 12)
184 #define ENETC_PPAUONTR 0x0410
185 #define ENETC_PPAUOFFTR 0x0414
186 #define ENETC_PTXMBAR 0x0608
187 #define ENETC_PCAPR0 0x0900
188 #define ENETC_PCAPR0_RXBDR(val) ((val) >> 24)
189 #define ENETC_PCAPR0_TXBDR(val) (((val) >> 16) & 0xff)
190 #define ENETC_PCAPR1 0x0904
191 #define ENETC_PSICFGR0(n) (0x0940 + (n) * 0xc) /* n = SI index */
192 #define ENETC_PSICFGR0_SET_TXBDR(val) ((val) & 0xff)
193 #define ENETC_PSICFGR0_SET_RXBDR(val) (((val) & 0xff) << 16)
194 #define ENETC_PSICFGR0_VTE BIT(12)
195 #define ENETC_PSICFGR0_SIVIE BIT(14)
196 #define ENETC_PSICFGR0_ASE BIT(15)
197 #define ENETC_PSICFGR0_SIVC(bmp) (((bmp) & 0xff) << 24) /* VLAN_TYPE */
198
199 #define ENETC_PTCCBSR0(n) (0x1110 + (n) * 8) /* n = 0 to 7*/
200 #define ENETC_CBSE BIT(31)
201 #define ENETC_CBS_BW_MASK GENMASK(6, 0)
202 #define ENETC_PTCCBSR1(n) (0x1114 + (n) * 8) /* n = 0 to 7*/
203 #define ENETC_RSSHASH_KEY_SIZE 40
204 #define ENETC_PRSSCAPR 0x1404
205 #define ENETC_PRSSCAPR_GET_NUM_RSS(val) (BIT((val) & 0xf) * 32)
206 #define ENETC_PRSSK(n) (0x1410 + (n) * 4) /* n = [0..9] */
207 #define ENETC_PSIVLANFMR 0x1700
208 #define ENETC_PSIVLANFMR_VS BIT(0)
209 #define ENETC_PRFSMR 0x1800
210 #define ENETC_PRFSMR_RFSE BIT(31)
211 #define ENETC_PRFSCAPR 0x1804
212 #define ENETC_PRFSCAPR_GET_NUM_RFS(val) ((((val) & 0xf) + 1) * 16)
213 #define ENETC_PSIRFSCFGR(n) (0x1814 + (n) * 4) /* n = SI index */
214 #define ENETC_PFPMR 0x1900
215 #define ENETC_PFPMR_PMACE BIT(1)
216 #define ENETC_PFPMR_MWLM BIT(0)
217 #define ENETC_EMDIO_BASE 0x1c00
218 #define ENETC_PSIUMHFR0(n, err) (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
219 #define ENETC_PSIUMHFR1(n) (0x1d04 + (n) * 0x10)
220 #define ENETC_PSIMMHFR0(n, err) (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
221 #define ENETC_PSIMMHFR1(n) (0x1d0c + (n) * 0x10)
222 #define ENETC_PSIVHFR0(n) (0x1e00 + (n) * 8) /* n = SI index */
223 #define ENETC_PSIVHFR1(n) (0x1e04 + (n) * 8) /* n = SI index */
224 #define ENETC_MMCSR 0x1f00
225 #define ENETC_MMCSR_ME BIT(16)
226 #define ENETC_PTCMSDUR(n) (0x2020 + (n) * 4) /* n = TC index [0..7] */
227
228 #define ENETC_PM0_CMD_CFG 0x8008
229 #define ENETC_PM1_CMD_CFG 0x9008
230 #define ENETC_PM0_TX_EN BIT(0)
231 #define ENETC_PM0_RX_EN BIT(1)
232 #define ENETC_PM0_PROMISC BIT(4)
233 #define ENETC_PM0_PAUSE_IGN BIT(8)
234 #define ENETC_PM0_CMD_XGLP BIT(10)
235 #define ENETC_PM0_CMD_TXP BIT(11)
236 #define ENETC_PM0_CMD_PHY_TX_EN BIT(15)
237 #define ENETC_PM0_CMD_SFD BIT(21)
238 #define ENETC_PM0_MAXFRM 0x8014
239 #define ENETC_SET_TX_MTU(val) ((val) << 16)
240 #define ENETC_SET_MAXFRM(val) ((val) & 0xffff)
241 #define ENETC_PM0_RX_FIFO 0x801c
242 #define ENETC_PM0_RX_FIFO_VAL 1
243
244 #define ENETC_PM_IMDIO_BASE 0x8030
245
246 #define ENETC_PM0_PAUSE_QUANTA 0x8054
247 #define ENETC_PM0_PAUSE_THRESH 0x8064
248 #define ENETC_PM1_PAUSE_QUANTA 0x9054
249 #define ENETC_PM1_PAUSE_THRESH 0x9064
250
251 #define ENETC_PM0_SINGLE_STEP 0x80c0
252 #define ENETC_PM1_SINGLE_STEP 0x90c0
253 #define ENETC_PM0_SINGLE_STEP_CH BIT(7)
254 #define ENETC_PM0_SINGLE_STEP_EN BIT(31)
255 #define ENETC_SET_SINGLE_STEP_OFFSET(v) (((v) & 0xff) << 8)
256
257 #define ENETC_PM0_IF_MODE 0x8300
258 #define ENETC_PM0_IFM_RG BIT(2)
259 #define ENETC_PM0_IFM_RLP (BIT(5) | BIT(11))
260 #define ENETC_PM0_IFM_EN_AUTO BIT(15)
261 #define ENETC_PM0_IFM_SSP_MASK GENMASK(14, 13)
262 #define ENETC_PM0_IFM_SSP_1000 (2 << 13)
263 #define ENETC_PM0_IFM_SSP_100 (0 << 13)
264 #define ENETC_PM0_IFM_SSP_10 (1 << 13)
265 #define ENETC_PM0_IFM_FULL_DPX BIT(12)
266 #define ENETC_PM0_IFM_IFMODE_MASK GENMASK(1, 0)
267 #define ENETC_PM0_IFM_IFMODE_XGMII 0
268 #define ENETC_PM0_IFM_IFMODE_GMII 2
269 #define ENETC_PSIDCAPR 0x1b08
270 #define ENETC_PSIDCAPR_MSK GENMASK(15, 0)
271 #define ENETC_PSFCAPR 0x1b18
272 #define ENETC_PSFCAPR_MSK GENMASK(15, 0)
273 #define ENETC_PSGCAPR 0x1b28
274 #define ENETC_PSGCAPR_GCL_MSK GENMASK(18, 16)
275 #define ENETC_PSGCAPR_SGIT_MSK GENMASK(15, 0)
276 #define ENETC_PFMCAPR 0x1b38
277 #define ENETC_PFMCAPR_MSK GENMASK(15, 0)
278
279 /* Port MAC counters: Port MAC 0 corresponds to the eMAC and
280 * Port MAC 1 to the pMAC.
281 */
282 #define ENETC_PM_REOCT(mac) (0x8100 + 0x1000 * (mac))
283 #define ENETC_PM_RALN(mac) (0x8110 + 0x1000 * (mac))
284 #define ENETC_PM_RXPF(mac) (0x8118 + 0x1000 * (mac))
285 #define ENETC_PM_RFRM(mac) (0x8120 + 0x1000 * (mac))
286 #define ENETC_PM_RFCS(mac) (0x8128 + 0x1000 * (mac))
287 #define ENETC_PM_RVLAN(mac) (0x8130 + 0x1000 * (mac))
288 #define ENETC_PM_RERR(mac) (0x8138 + 0x1000 * (mac))
289 #define ENETC_PM_RUCA(mac) (0x8140 + 0x1000 * (mac))
290 #define ENETC_PM_RMCA(mac) (0x8148 + 0x1000 * (mac))
291 #define ENETC_PM_RBCA(mac) (0x8150 + 0x1000 * (mac))
292 #define ENETC_PM_RDRP(mac) (0x8158 + 0x1000 * (mac))
293 #define ENETC_PM_RPKT(mac) (0x8160 + 0x1000 * (mac))
294 #define ENETC_PM_RUND(mac) (0x8168 + 0x1000 * (mac))
295 #define ENETC_PM_R64(mac) (0x8170 + 0x1000 * (mac))
296 #define ENETC_PM_R127(mac) (0x8178 + 0x1000 * (mac))
297 #define ENETC_PM_R255(mac) (0x8180 + 0x1000 * (mac))
298 #define ENETC_PM_R511(mac) (0x8188 + 0x1000 * (mac))
299 #define ENETC_PM_R1023(mac) (0x8190 + 0x1000 * (mac))
300 #define ENETC_PM_R1522(mac) (0x8198 + 0x1000 * (mac))
301 #define ENETC_PM_R1523X(mac) (0x81A0 + 0x1000 * (mac))
302 #define ENETC_PM_ROVR(mac) (0x81A8 + 0x1000 * (mac))
303 #define ENETC_PM_RJBR(mac) (0x81B0 + 0x1000 * (mac))
304 #define ENETC_PM_RFRG(mac) (0x81B8 + 0x1000 * (mac))
305 #define ENETC_PM_RCNP(mac) (0x81C0 + 0x1000 * (mac))
306 #define ENETC_PM_RDRNTP(mac) (0x81C8 + 0x1000 * (mac))
307 #define ENETC_PM_TEOCT(mac) (0x8200 + 0x1000 * (mac))
308 #define ENETC_PM_TOCT(mac) (0x8208 + 0x1000 * (mac))
309 #define ENETC_PM_TCRSE(mac) (0x8210 + 0x1000 * (mac))
310 #define ENETC_PM_TXPF(mac) (0x8218 + 0x1000 * (mac))
311 #define ENETC_PM_TFRM(mac) (0x8220 + 0x1000 * (mac))
312 #define ENETC_PM_TFCS(mac) (0x8228 + 0x1000 * (mac))
313 #define ENETC_PM_TVLAN(mac) (0x8230 + 0x1000 * (mac))
314 #define ENETC_PM_TERR(mac) (0x8238 + 0x1000 * (mac))
315 #define ENETC_PM_TUCA(mac) (0x8240 + 0x1000 * (mac))
316 #define ENETC_PM_TMCA(mac) (0x8248 + 0x1000 * (mac))
317 #define ENETC_PM_TBCA(mac) (0x8250 + 0x1000 * (mac))
318 #define ENETC_PM_TPKT(mac) (0x8260 + 0x1000 * (mac))
319 #define ENETC_PM_TUND(mac) (0x8268 + 0x1000 * (mac))
320 #define ENETC_PM_T64(mac) (0x8270 + 0x1000 * (mac))
321 #define ENETC_PM_T127(mac) (0x8278 + 0x1000 * (mac))
322 #define ENETC_PM_T255(mac) (0x8280 + 0x1000 * (mac))
323 #define ENETC_PM_T511(mac) (0x8288 + 0x1000 * (mac))
324 #define ENETC_PM_T1023(mac) (0x8290 + 0x1000 * (mac))
325 #define ENETC_PM_T1522(mac) (0x8298 + 0x1000 * (mac))
326 #define ENETC_PM_T1523X(mac) (0x82A0 + 0x1000 * (mac))
327 #define ENETC_PM_TCNP(mac) (0x82C0 + 0x1000 * (mac))
328 #define ENETC_PM_TDFR(mac) (0x82D0 + 0x1000 * (mac))
329 #define ENETC_PM_TMCOL(mac) (0x82D8 + 0x1000 * (mac))
330 #define ENETC_PM_TSCOL(mac) (0x82E0 + 0x1000 * (mac))
331 #define ENETC_PM_TLCOL(mac) (0x82E8 + 0x1000 * (mac))
332 #define ENETC_PM_TECOL(mac) (0x82F0 + 0x1000 * (mac))
333
334 /* Port counters */
335 #define ENETC_PICDR(n) (0x0700 + (n) * 8) /* n = [0..3] */
336 #define ENETC_PBFDSIR 0x0810
337 #define ENETC_PFDMSAPR 0x0814
338 #define ENETC_UFDMF 0x1680
339 #define ENETC_MFDMF 0x1684
340 #define ENETC_PUFDVFR 0x1780
341 #define ENETC_PMFDVFR 0x1784
342 #define ENETC_PBFDVFR 0x1788
343
344 /** Global regs, offset: 2_0000h */
345 #define ENETC_GLOBAL_BASE 0x20000
346 #define ENETC_G_EIPBRR0 0x0bf8
347 #define ENETC_G_EIPBRR1 0x0bfc
348 #define ENETC_G_EPFBLPR(n) (0xd00 + 4 * (n))
349 #define ENETC_G_EPFBLPR1_XGMII 0x80000000
350
351 /* PCI device info */
352 struct enetc_hw {
353 /* SI registers, used by all PCI functions */
354 void __iomem *reg;
355 /* Port registers, PF only */
356 void __iomem *port;
357 /* IP global registers, PF only */
358 void __iomem *global;
359 };
360
361 /* ENETC register accessors */
362
363 /* MDIO issue workaround (on LS1028A) -
364 * Due to a hardware issue, an access to MDIO registers
365 * that is concurrent with other ENETC register accesses
366 * may lead to the MDIO access being dropped or corrupted.
367 * To protect the MDIO accesses a readers-writers locking
368 * scheme is used, where the MDIO register accesses are
369 * protected by write locks to insure exclusivity, while
370 * the remaining ENETC registers are accessed under read
371 * locks since they only compete with MDIO accesses.
372 */
373 extern rwlock_t enetc_mdio_lock;
374
375 /* use this locking primitive only on the fast datapath to
376 * group together multiple non-MDIO register accesses to
377 * minimize the overhead of the lock
378 */
enetc_lock_mdio(void)379 static inline void enetc_lock_mdio(void)
380 {
381 read_lock(&enetc_mdio_lock);
382 }
383
enetc_unlock_mdio(void)384 static inline void enetc_unlock_mdio(void)
385 {
386 read_unlock(&enetc_mdio_lock);
387 }
388
389 /* use these accessors only on the fast datapath under
390 * the enetc_lock_mdio() locking primitive to minimize
391 * the overhead of the lock
392 */
enetc_rd_reg_hot(void __iomem * reg)393 static inline u32 enetc_rd_reg_hot(void __iomem *reg)
394 {
395 lockdep_assert_held(&enetc_mdio_lock);
396
397 return ioread32(reg);
398 }
399
enetc_wr_reg_hot(void __iomem * reg,u32 val)400 static inline void enetc_wr_reg_hot(void __iomem *reg, u32 val)
401 {
402 lockdep_assert_held(&enetc_mdio_lock);
403
404 iowrite32(val, reg);
405 }
406
407 /* internal helpers for the MDIO w/a */
_enetc_rd_reg_wa(void __iomem * reg)408 static inline u32 _enetc_rd_reg_wa(void __iomem *reg)
409 {
410 u32 val;
411
412 enetc_lock_mdio();
413 val = ioread32(reg);
414 enetc_unlock_mdio();
415
416 return val;
417 }
418
_enetc_wr_reg_wa(void __iomem * reg,u32 val)419 static inline void _enetc_wr_reg_wa(void __iomem *reg, u32 val)
420 {
421 enetc_lock_mdio();
422 iowrite32(val, reg);
423 enetc_unlock_mdio();
424 }
425
_enetc_rd_mdio_reg_wa(void __iomem * reg)426 static inline u32 _enetc_rd_mdio_reg_wa(void __iomem *reg)
427 {
428 unsigned long flags;
429 u32 val;
430
431 write_lock_irqsave(&enetc_mdio_lock, flags);
432 val = ioread32(reg);
433 write_unlock_irqrestore(&enetc_mdio_lock, flags);
434
435 return val;
436 }
437
_enetc_wr_mdio_reg_wa(void __iomem * reg,u32 val)438 static inline void _enetc_wr_mdio_reg_wa(void __iomem *reg, u32 val)
439 {
440 unsigned long flags;
441
442 write_lock_irqsave(&enetc_mdio_lock, flags);
443 iowrite32(val, reg);
444 write_unlock_irqrestore(&enetc_mdio_lock, flags);
445 }
446
447 #ifdef ioread64
_enetc_rd_reg64(void __iomem * reg)448 static inline u64 _enetc_rd_reg64(void __iomem *reg)
449 {
450 return ioread64(reg);
451 }
452 #else
453 /* using this to read out stats on 32b systems */
_enetc_rd_reg64(void __iomem * reg)454 static inline u64 _enetc_rd_reg64(void __iomem *reg)
455 {
456 u32 low, high, tmp;
457
458 do {
459 high = ioread32(reg + 4);
460 low = ioread32(reg);
461 tmp = ioread32(reg + 4);
462 } while (high != tmp);
463
464 return le64_to_cpu((__le64)high << 32 | low);
465 }
466 #endif
467
_enetc_rd_reg64_wa(void __iomem * reg)468 static inline u64 _enetc_rd_reg64_wa(void __iomem *reg)
469 {
470 u64 val;
471
472 enetc_lock_mdio();
473 val = _enetc_rd_reg64(reg);
474 enetc_unlock_mdio();
475
476 return val;
477 }
478
479 /* general register accessors */
480 #define enetc_rd_reg(reg) _enetc_rd_reg_wa((reg))
481 #define enetc_wr_reg(reg, val) _enetc_wr_reg_wa((reg), (val))
482 #define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off))
483 #define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val)
484 #define enetc_rd_hot(hw, off) enetc_rd_reg_hot((hw)->reg + (off))
485 #define enetc_wr_hot(hw, off, val) enetc_wr_reg_hot((hw)->reg + (off), val)
486 #define enetc_rd64(hw, off) _enetc_rd_reg64_wa((hw)->reg + (off))
487 /* port register accessors - PF only */
488 #define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off))
489 #define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val)
490 #define enetc_port_rd_mdio(hw, off) _enetc_rd_mdio_reg_wa((hw)->port + (off))
491 #define enetc_port_wr_mdio(hw, off, val) _enetc_wr_mdio_reg_wa(\
492 (hw)->port + (off), val)
493 /* global register accessors - PF only */
494 #define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off))
495 #define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val)
496 /* BDR register accessors, see ENETC_BDR() */
497 #define enetc_bdr_rd(hw, t, n, off) \
498 enetc_rd(hw, ENETC_BDR(t, n, off))
499 #define enetc_bdr_wr(hw, t, n, off, val) \
500 enetc_wr(hw, ENETC_BDR(t, n, off), val)
501 #define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off)
502 #define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off)
503 #define enetc_txbdr_wr(hw, n, off, val) \
504 enetc_bdr_wr(hw, TX, n, off, val)
505 #define enetc_rxbdr_wr(hw, n, off, val) \
506 enetc_bdr_wr(hw, RX, n, off, val)
507
508 /* Buffer Descriptors (BD) */
509 union enetc_tx_bd {
510 struct {
511 __le64 addr;
512 __le16 buf_len;
513 __le16 frm_len;
514 union {
515 struct {
516 u8 reserved[3];
517 u8 flags;
518 }; /* default layout */
519 __le32 txstart;
520 __le32 lstatus;
521 };
522 };
523 struct {
524 __le32 tstamp;
525 __le16 tpid;
526 __le16 vid;
527 u8 reserved[6];
528 u8 e_flags;
529 u8 flags;
530 } ext; /* Tx BD extension */
531 struct {
532 __le32 tstamp;
533 u8 reserved[10];
534 u8 status;
535 u8 flags;
536 } wb; /* writeback descriptor */
537 };
538
539 enum enetc_txbd_flags {
540 ENETC_TXBD_FLAGS_RES0 = BIT(0), /* reserved */
541 ENETC_TXBD_FLAGS_TSE = BIT(1),
542 ENETC_TXBD_FLAGS_W = BIT(2),
543 ENETC_TXBD_FLAGS_RES3 = BIT(3), /* reserved */
544 ENETC_TXBD_FLAGS_TXSTART = BIT(4),
545 ENETC_TXBD_FLAGS_EX = BIT(6),
546 ENETC_TXBD_FLAGS_F = BIT(7)
547 };
548 #define ENETC_TXBD_STATS_WIN BIT(7)
549 #define ENETC_TXBD_TXSTART_MASK GENMASK(24, 0)
550 #define ENETC_TXBD_FLAGS_OFFSET 24
551
enetc_txbd_set_tx_start(u64 tx_start,u8 flags)552 static inline __le32 enetc_txbd_set_tx_start(u64 tx_start, u8 flags)
553 {
554 u32 temp;
555
556 temp = (tx_start >> 5 & ENETC_TXBD_TXSTART_MASK) |
557 (flags << ENETC_TXBD_FLAGS_OFFSET);
558
559 return cpu_to_le32(temp);
560 }
561
enetc_clear_tx_bd(union enetc_tx_bd * txbd)562 static inline void enetc_clear_tx_bd(union enetc_tx_bd *txbd)
563 {
564 memset(txbd, 0, sizeof(*txbd));
565 }
566
567 /* Extension flags */
568 #define ENETC_TXBD_E_FLAGS_VLAN_INS BIT(0)
569 #define ENETC_TXBD_E_FLAGS_ONE_STEP_PTP BIT(1)
570 #define ENETC_TXBD_E_FLAGS_TWO_STEP_PTP BIT(2)
571
572 union enetc_rx_bd {
573 struct {
574 __le64 addr;
575 u8 reserved[8];
576 } w;
577 struct {
578 __le16 inet_csum;
579 __le16 parse_summary;
580 __le32 rss_hash;
581 __le16 buf_len;
582 __le16 vlan_opt;
583 union {
584 struct {
585 __le16 flags;
586 __le16 error;
587 };
588 __le32 lstatus;
589 };
590 } r;
591 struct {
592 __le32 tstamp;
593 u8 reserved[12];
594 } ext;
595 };
596
597 #define ENETC_RXBD_LSTATUS_R BIT(30)
598 #define ENETC_RXBD_LSTATUS_F BIT(31)
599 #define ENETC_RXBD_ERR_MASK 0xff
600 #define ENETC_RXBD_LSTATUS(flags) ((flags) << 16)
601 #define ENETC_RXBD_FLAG_VLAN BIT(9)
602 #define ENETC_RXBD_FLAG_TSTMP BIT(10)
603 #define ENETC_RXBD_FLAG_TPID GENMASK(1, 0)
604
605 #define ENETC_MAC_ADDR_FILT_CNT 8 /* # of supported entries per port */
606 #define EMETC_MAC_ADDR_FILT_RES 3 /* # of reserved entries at the beginning */
607 #define ENETC_MAX_NUM_VFS 2
608
609 #define ENETC_CBD_FLAGS_SF BIT(7) /* short format */
610 #define ENETC_CBD_STATUS_MASK 0xf
611
612 struct enetc_cmd_rfse {
613 u8 smac_h[6];
614 u8 smac_m[6];
615 u8 dmac_h[6];
616 u8 dmac_m[6];
617 __be32 sip_h[4];
618 __be32 sip_m[4];
619 __be32 dip_h[4];
620 __be32 dip_m[4];
621 u16 ethtype_h;
622 u16 ethtype_m;
623 u16 ethtype4_h;
624 u16 ethtype4_m;
625 u16 sport_h;
626 u16 sport_m;
627 u16 dport_h;
628 u16 dport_m;
629 u16 vlan_h;
630 u16 vlan_m;
631 u8 proto_h;
632 u8 proto_m;
633 u16 flags;
634 u16 result;
635 u16 mode;
636 };
637
638 #define ENETC_RFSE_EN BIT(15)
639 #define ENETC_RFSE_MODE_BD 2
640
enetc_load_primary_mac_addr(struct enetc_hw * hw,struct net_device * ndev)641 static inline void enetc_load_primary_mac_addr(struct enetc_hw *hw,
642 struct net_device *ndev)
643 {
644 u8 addr[ETH_ALEN] __aligned(4);
645
646 *(u32 *)addr = __raw_readl(hw->reg + ENETC_SIPMAR0);
647 *(u16 *)(addr + 4) = __raw_readw(hw->reg + ENETC_SIPMAR1);
648 eth_hw_addr_set(ndev, addr);
649 }
650
651 #define ENETC_SI_INT_IDX 0
652 /* base index for Rx/Tx interrupts */
653 #define ENETC_BDR_INT_BASE_IDX 1
654
655 /* Messaging */
656
657 /* Command completion status */
658 enum enetc_msg_cmd_status {
659 ENETC_MSG_CMD_STATUS_OK,
660 ENETC_MSG_CMD_STATUS_FAIL
661 };
662
663 /* VSI-PSI command message types */
664 enum enetc_msg_cmd_type {
665 ENETC_MSG_CMD_MNG_MAC = 1, /* manage MAC address */
666 ENETC_MSG_CMD_MNG_RX_MAC_FILTER,/* manage RX MAC table */
667 ENETC_MSG_CMD_MNG_RX_VLAN_FILTER /* manage RX VLAN table */
668 };
669
670 /* VSI-PSI command action types */
671 enum enetc_msg_cmd_action_type {
672 ENETC_MSG_CMD_MNG_ADD = 1,
673 ENETC_MSG_CMD_MNG_REMOVE
674 };
675
676 /* PSI-VSI command header format */
677 struct enetc_msg_cmd_header {
678 u16 type; /* command class type */
679 u16 id; /* denotes the specific required action */
680 };
681
682 /* Common H/W utility functions */
683
enetc_bdr_enable_rxvlan(struct enetc_hw * hw,int idx,bool en)684 static inline void enetc_bdr_enable_rxvlan(struct enetc_hw *hw, int idx,
685 bool en)
686 {
687 u32 val = enetc_rxbdr_rd(hw, idx, ENETC_RBMR);
688
689 val = (val & ~ENETC_RBMR_VTE) | (en ? ENETC_RBMR_VTE : 0);
690 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, val);
691 }
692
enetc_bdr_enable_txvlan(struct enetc_hw * hw,int idx,bool en)693 static inline void enetc_bdr_enable_txvlan(struct enetc_hw *hw, int idx,
694 bool en)
695 {
696 u32 val = enetc_txbdr_rd(hw, idx, ENETC_TBMR);
697
698 val = (val & ~ENETC_TBMR_VIH) | (en ? ENETC_TBMR_VIH : 0);
699 enetc_txbdr_wr(hw, idx, ENETC_TBMR, val);
700 }
701
enetc_set_bdr_prio(struct enetc_hw * hw,int bdr_idx,int prio)702 static inline void enetc_set_bdr_prio(struct enetc_hw *hw, int bdr_idx,
703 int prio)
704 {
705 u32 val = enetc_txbdr_rd(hw, bdr_idx, ENETC_TBMR);
706
707 val &= ~ENETC_TBMR_PRIO_MASK;
708 val |= ENETC_TBMR_SET_PRIO(prio);
709 enetc_txbdr_wr(hw, bdr_idx, ENETC_TBMR, val);
710 }
711
712 enum bdcr_cmd_class {
713 BDCR_CMD_UNSPEC = 0,
714 BDCR_CMD_MAC_FILTER,
715 BDCR_CMD_VLAN_FILTER,
716 BDCR_CMD_RSS,
717 BDCR_CMD_RFS,
718 BDCR_CMD_PORT_GCL,
719 BDCR_CMD_RECV_CLASSIFIER,
720 BDCR_CMD_STREAM_IDENTIFY,
721 BDCR_CMD_STREAM_FILTER,
722 BDCR_CMD_STREAM_GCL,
723 BDCR_CMD_FLOW_METER,
724 __BDCR_CMD_MAX_LEN,
725 BDCR_CMD_MAX_LEN = __BDCR_CMD_MAX_LEN - 1,
726 };
727
728 /* class 5, command 0 */
729 struct tgs_gcl_conf {
730 u8 atc; /* init gate value */
731 u8 res[7];
732 struct {
733 u8 res1[4];
734 __le16 acl_len;
735 u8 res2[2];
736 };
737 };
738
739 /* gate control list entry */
740 struct gce {
741 __le32 period;
742 u8 gate;
743 u8 res[3];
744 };
745
746 /* tgs_gcl_conf address point to this data space */
747 struct tgs_gcl_data {
748 __le32 btl;
749 __le32 bth;
750 __le32 ct;
751 __le32 cte;
752 struct gce entry[];
753 };
754
755 /* class 7, command 0, Stream Identity Entry Configuration */
756 struct streamid_conf {
757 __le32 stream_handle; /* init gate value */
758 __le32 iports;
759 u8 id_type;
760 u8 oui[3];
761 u8 res[3];
762 u8 en;
763 };
764
765 #define ENETC_CBDR_SID_VID_MASK 0xfff
766 #define ENETC_CBDR_SID_VIDM BIT(12)
767 #define ENETC_CBDR_SID_TG_MASK 0xc000
768 /* streamid_conf address point to this data space */
769 struct streamid_data {
770 union {
771 u8 dmac[6];
772 u8 smac[6];
773 };
774 u16 vid_vidm_tg;
775 };
776
777 #define ENETC_CBDR_SFI_PRI_MASK 0x7
778 #define ENETC_CBDR_SFI_PRIM BIT(3)
779 #define ENETC_CBDR_SFI_BLOV BIT(4)
780 #define ENETC_CBDR_SFI_BLEN BIT(5)
781 #define ENETC_CBDR_SFI_MSDUEN BIT(6)
782 #define ENETC_CBDR_SFI_FMITEN BIT(7)
783 #define ENETC_CBDR_SFI_ENABLE BIT(7)
784 /* class 8, command 0, Stream Filter Instance, Short Format */
785 struct sfi_conf {
786 __le32 stream_handle;
787 u8 multi;
788 u8 res[2];
789 u8 sthm;
790 /* Max Service Data Unit or Flow Meter Instance Table index.
791 * Depending on the value of FLT this represents either Max
792 * Service Data Unit (max frame size) allowed by the filter
793 * entry or is an index into the Flow Meter Instance table
794 * index identifying the policer which will be used to police
795 * it.
796 */
797 __le16 fm_inst_table_index;
798 __le16 msdu;
799 __le16 sg_inst_table_index;
800 u8 res1[2];
801 __le32 input_ports;
802 u8 res2[3];
803 u8 en;
804 };
805
806 /* class 8, command 2 stream Filter Instance status query short format
807 * command no need structure define
808 * Stream Filter Instance Query Statistics Response data
809 */
810 struct sfi_counter_data {
811 u32 matchl;
812 u32 matchh;
813 u32 msdu_dropl;
814 u32 msdu_droph;
815 u32 stream_gate_dropl;
816 u32 stream_gate_droph;
817 u32 flow_meter_dropl;
818 u32 flow_meter_droph;
819 };
820
821 #define ENETC_CBDR_SGI_OIPV_MASK 0x7
822 #define ENETC_CBDR_SGI_OIPV_EN BIT(3)
823 #define ENETC_CBDR_SGI_CGTST BIT(6)
824 #define ENETC_CBDR_SGI_OGTST BIT(7)
825 #define ENETC_CBDR_SGI_CFG_CHG BIT(1)
826 #define ENETC_CBDR_SGI_CFG_PND BIT(2)
827 #define ENETC_CBDR_SGI_OEX BIT(4)
828 #define ENETC_CBDR_SGI_OEXEN BIT(5)
829 #define ENETC_CBDR_SGI_IRX BIT(6)
830 #define ENETC_CBDR_SGI_IRXEN BIT(7)
831 #define ENETC_CBDR_SGI_ACLLEN_MASK 0x3
832 #define ENETC_CBDR_SGI_OCLLEN_MASK 0xc
833 #define ENETC_CBDR_SGI_EN BIT(7)
834 /* class 9, command 0, Stream Gate Instance Table, Short Format
835 * class 9, command 2, Stream Gate Instance Table entry query write back
836 * Short Format
837 */
838 struct sgi_table {
839 u8 res[8];
840 u8 oipv;
841 u8 res0[2];
842 u8 ocgtst;
843 u8 res1[7];
844 u8 gset;
845 u8 oacl_len;
846 u8 res2[2];
847 u8 en;
848 };
849
850 #define ENETC_CBDR_SGI_AIPV_MASK 0x7
851 #define ENETC_CBDR_SGI_AIPV_EN BIT(3)
852 #define ENETC_CBDR_SGI_AGTST BIT(7)
853
854 /* class 9, command 1, Stream Gate Control List, Long Format */
855 struct sgcl_conf {
856 u8 aipv;
857 u8 res[2];
858 u8 agtst;
859 u8 res1[4];
860 union {
861 struct {
862 u8 res2[4];
863 u8 acl_len;
864 u8 res3[3];
865 };
866 u8 cct[8]; /* Config change time */
867 };
868 };
869
870 #define ENETC_CBDR_SGL_IOMEN BIT(0)
871 #define ENETC_CBDR_SGL_IPVEN BIT(3)
872 #define ENETC_CBDR_SGL_GTST BIT(4)
873 #define ENETC_CBDR_SGL_IPV_MASK 0xe
874 /* Stream Gate Control List Entry */
875 struct sgce {
876 u32 interval;
877 u8 msdu[3];
878 u8 multi;
879 };
880
881 /* stream control list class 9 , cmd 1 data buffer */
882 struct sgcl_data {
883 u32 btl;
884 u32 bth;
885 u32 ct;
886 u32 cte;
887 struct sgce sgcl[];
888 };
889
890 #define ENETC_CBDR_FMI_MR BIT(0)
891 #define ENETC_CBDR_FMI_MREN BIT(1)
892 #define ENETC_CBDR_FMI_DOY BIT(2)
893 #define ENETC_CBDR_FMI_CM BIT(3)
894 #define ENETC_CBDR_FMI_CF BIT(4)
895 #define ENETC_CBDR_FMI_NDOR BIT(5)
896 #define ENETC_CBDR_FMI_OALEN BIT(6)
897 #define ENETC_CBDR_FMI_IRFPP_MASK GENMASK(4, 0)
898
899 /* class 10: command 0/1, Flow Meter Instance Set, short Format */
900 struct fmi_conf {
901 __le32 cir;
902 __le32 cbs;
903 __le32 eir;
904 __le32 ebs;
905 u8 conf;
906 u8 res1;
907 u8 ir_fpp;
908 u8 res2[4];
909 u8 en;
910 };
911
912 struct enetc_cbd {
913 union{
914 struct sfi_conf sfi_conf;
915 struct sgi_table sgi_table;
916 struct fmi_conf fmi_conf;
917 struct {
918 __le32 addr[2];
919 union {
920 __le32 opt[4];
921 struct tgs_gcl_conf gcl_conf;
922 struct streamid_conf sid_set;
923 struct sgcl_conf sgcl_conf;
924 };
925 }; /* Long format */
926 __le32 data[6];
927 };
928 __le16 index;
929 __le16 length;
930 u8 cmd;
931 u8 cls;
932 u8 _res;
933 u8 status_flags;
934 };
935
936 #define ENETC_CLK 400000000ULL
enetc_cycles_to_usecs(u32 cycles)937 static inline u32 enetc_cycles_to_usecs(u32 cycles)
938 {
939 return (u32)div_u64(cycles * 1000000ULL, ENETC_CLK);
940 }
941
enetc_usecs_to_cycles(u32 usecs)942 static inline u32 enetc_usecs_to_cycles(u32 usecs)
943 {
944 return (u32)div_u64(usecs * ENETC_CLK, 1000000ULL);
945 }
946
947 /* port time gating control register */
948 #define ENETC_PTGCR 0x11a00
949 #define ENETC_PTGCR_TGE BIT(31)
950 #define ENETC_PTGCR_TGPE BIT(30)
951
952 /* Port time gating capability register */
953 #define ENETC_PTGCAPR 0x11a08
954 #define ENETC_PTGCAPR_MAX_GCL_LEN_MASK GENMASK(15, 0)
955
956 /* Port time specific departure */
957 #define ENETC_PTCTSDR(n) (0x1210 + 4 * (n))
958 #define ENETC_TSDE BIT(31)
959
960 /* PSFP setting */
961 #define ENETC_PPSFPMR 0x11b00
962 #define ENETC_PPSFPMR_PSFPEN BIT(0)
963 #define ENETC_PPSFPMR_VS BIT(1)
964 #define ENETC_PPSFPMR_PVC BIT(2)
965 #define ENETC_PPSFPMR_PVZC BIT(3)
966