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Searched refs:dsc (Results 1 – 25 of 91) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_dsc.c32 static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc) in dpu_hw_dsc_disable() argument
34 struct dpu_hw_blk_reg_map *c = &dsc->hw; in dpu_hw_dsc_disable()
40 struct drm_dsc_config *dsc, in dpu_hw_dsc_config() argument
55 slice_last_group_size = 3 - (dsc->slice_width % 3); in dpu_hw_dsc_config()
59 data |= (dsc->bits_per_pixel << 8); in dpu_hw_dsc_config()
60 data |= (dsc->block_pred_enable << 7); in dpu_hw_dsc_config()
61 data |= (dsc->line_buf_depth << 3); in dpu_hw_dsc_config()
62 data |= (dsc->simple_422 << 2); in dpu_hw_dsc_config()
63 data |= (dsc->convert_rgb << 1); in dpu_hw_dsc_config()
64 data |= dsc->bits_per_component; in dpu_hw_dsc_config()
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Ddpu_hw_dsc.h34 struct drm_dsc_config *dsc,
44 struct drm_dsc_config *dsc);
73 void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
Ddpu_encoder.c211 struct drm_dsc_config *dsc; member
539 if (dpu_enc->dsc) in dpu_encoder_use_dsc_merge()
585 if (dpu_enc->dsc) { in dpu_encoder_get_topology()
1070 if (dpu_enc->dsc) { in dpu_encoder_virt_atomic_mode_set()
1794 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc, in dpu_encoder_dsc_initial_line_calc() argument
1799 soft_slice_per_enc = enc_ip_width / dsc->slice_width; in dpu_encoder_dsc_initial_line_calc()
1811 ssm_delay = ((dsc->bits_per_component < 10) ? 84 : 92); in dpu_encoder_dsc_initial_line_calc()
1812 total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47; in dpu_encoder_dsc_initial_line_calc()
1815 return DIV_ROUND_UP(total_pixels, dsc->slice_width); in dpu_encoder_dsc_initial_line_calc()
1820 struct drm_dsc_config *dsc, in dpu_encoder_dsc_pipe_cfg() argument
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/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_vdsc.c456 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
457 u16 compressed_bpp = pipe_config->dsc.compressed_bpp; in intel_dsc_compute_params()
464 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
582 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_dsc_pps_configure()
588 u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; in intel_dsc_pps_configure()
617 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
624 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
641 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
648 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
666 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
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Dintel_bios.c69 struct dsc_compression_parameters_entry *dsc; member
2120 devdata->dsc = kmemdup(&params->data[index], in parse_compression_parameters()
2121 sizeof(*devdata->dsc), GFP_KERNEL); in parse_compression_parameters()
2646 devdata->dsc != NULL); in print_ddi_port()
3211 kfree(devdata->dsc); in intel_bios_driver_remove()
3428 struct dsc_compression_parameters_entry *dsc, in fill_dsc() argument
3431 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in fill_dsc()
3434 vdsc_cfg->dsc_version_major = dsc->version_major; in fill_dsc()
3435 vdsc_cfg->dsc_version_minor = dsc->version_minor; in fill_dsc()
3437 if (dsc->support_12bpc && dsc_max_bpc >= 12) in fill_dsc()
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Dicl_dsi.c344 if (crtc_state->dsc.compression_enable) in afe_clk()
345 bpp = crtc_state->dsc.compressed_bpp; in afe_clk()
764 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
904 if (crtc_state->dsc.compression_enable) { in gen11_dsi_set_transcoder_timings()
905 mul = crtc_state->dsc.compressed_bpp; in gen11_dsi_set_transcoder_timings()
928 if (crtc_state->dsc.compression_enable) in gen11_dsi_set_transcoder_timings()
929 bpp = crtc_state->dsc.compressed_bpp; in gen11_dsi_set_transcoder_timings()
1502 if (pipe_config->dsc.compressed_bpp) { in gen11_dsi_get_timings()
1503 int div = pipe_config->dsc.compressed_bpp; in gen11_dsi_get_timings()
1612 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dsc.c32 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps);
37 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_valu…
43 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
44 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *ds…
45 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
47 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc…
48 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
49 static void dsc2_disable(struct display_stream_compressor *dsc);
50 static void dsc2_disconnect(struct display_stream_compressor *dsc);
74 dsc->ctx->logger
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Ddcn20_resource.c1083 struct dcn20_dsc *dsc = in dcn20_dsc_create() local
1086 if (!dsc) { in dcn20_dsc_create()
1091 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); in dcn20_dsc_create()
1092 return &dsc->base; in dcn20_dsc_create()
1095 void dcn20_dsc_destroy(struct display_stream_compressor **dsc) in dcn20_dsc_destroy() argument
1097 kfree(container_of(*dsc, struct dcn20_dsc, base)); in dcn20_dsc_destroy()
1098 *dsc = NULL; in dcn20_dsc_destroy()
1325 struct display_stream_compressor **dsc, in dcn20_acquire_dsc() argument
1330 … display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; in dcn20_acquire_dsc()
1332 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */ in dcn20_acquire_dsc()
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Ddcn20_resource.h100 void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
131 struct display_stream_compressor **dsc);
145 struct display_stream_compressor **dsc,
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/
Ddcn314_hwseq.c99 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() local
104 ASSERT(dsc); in update_dsc_on_stream()
123 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
124 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
126 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in update_dsc_on_stream()
150 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); in update_dsc_on_stream()
152 ASSERT(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
153 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
224 if (pipe_ctx->stream_res.dsc) { in dcn314_update_odm()
231 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { in dcn314_update_odm()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/hw/
Ddsc.h99 void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
100 …bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cf…
101 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
103 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
105 void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
106 void (*dsc_disable)(struct display_stream_compressor *dsc);
107 void (*dsc_disconnect)(struct display_stream_compressor *dsc);
/linux-6.1.9/drivers/gpu/drm/msm/dsi/
Ddsi_host.c37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
164 struct drm_dsc_config *dsc; member
845 struct drm_dsc_config *dsc = msm_host->dsc; in dsi_update_dsc_timing() local
854 slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); in dsi_update_dsc_timing()
860 if (slice_per_intf > dsc->slice_count) in dsi_update_dsc_timing()
861 dsc->slice_count = 1; in dsi_update_dsc_timing()
863 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; in dsi_update_dsc_timing()
866 pkt_per_line = slice_per_intf / dsc->slice_count; in dsi_update_dsc_timing()
889 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); in dsi_update_dsc_timing()
931 if (msm_host->dsc) { in dsi_timing_setup()
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/linux-6.1.9/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c1356 struct display_stream_compressor *dsc; in dp_dsc_clock_en_read() local
1382 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_clock_en_read()
1383 if (dsc) in dp_dsc_clock_en_read()
1384 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_clock_en_read()
1547 struct display_stream_compressor *dsc; in dp_dsc_slice_width_read() local
1573 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_width_read()
1574 if (dsc) in dp_dsc_slice_width_read()
1575 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_slice_width_read()
1736 struct display_stream_compressor *dsc; in dp_dsc_slice_height_read() local
1762 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_height_read()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_hwseq.c1019 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() local
1024 ASSERT(dsc); in update_dsc_on_stream()
1043 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
1044 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
1046 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in update_dsc_on_stream()
1070 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); in update_dsc_on_stream()
1072 ASSERT(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
1073 odm_pipe->stream_res.dsc->funcs->dsc_disable(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
1146 if (pipe_ctx->stream_res.dsc) { in dcn32_update_odm()
1153 current_pipe_ctx->next_odm_pipe->stream_res.dsc) { in dcn32_update_odm()
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/linux-6.1.9/drivers/net/ethernet/broadcom/
Dsb1250-mac.c775 struct sbdmadscr *dsc; in sbdma_add_rcvbuffer() local
782 dsc = d->sbdma_addptr; in sbdma_add_rcvbuffer()
839 dsc->dscr_a = virt_to_phys(sb_new->data) | in sbdma_add_rcvbuffer()
842 dsc->dscr_a = virt_to_phys(sb_new->data) | in sbdma_add_rcvbuffer()
848 dsc->dscr_b = 0; in sbdma_add_rcvbuffer()
854 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; in sbdma_add_rcvbuffer()
889 struct sbdmadscr *dsc; in sbdma_add_txbuffer() local
897 dsc = d->sbdma_addptr; in sbdma_add_txbuffer()
928 dsc->dscr_a = phys | in sbdma_add_txbuffer()
937 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | in sbdma_add_txbuffer()
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/linux-6.1.9/include/linux/irqchip/
Dirq-partition-percpu.h28 struct irq_domain *partition_get_domain(struct partition_desc *dsc);
47 struct irq_domain *partition_get_domain(struct partition_desc *dsc) in partition_get_domain() argument
/linux-6.1.9/drivers/net/ethernet/mellanox/mlx5/core/
Den_stats.h36 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \ argument
37 (*(u64 *)((char *)ptr + dsc[i].offset))
38 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \ argument
39 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
40 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \ argument
41 (*(u32 *)((char *)ptr + dsc[i].offset))
42 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \ argument
43 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
/linux-6.1.9/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
Dipsec_stats.c50 #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ argument
51 atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))
Dktls_stats.c50 #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ argument
51 atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/
Ddc_dsc.h63 const struct display_stream_compressor *dsc,
72 const struct display_stream_compressor *dsc,
/linux-6.1.9/arch/mips/mm/
Dcerr-sb1.c466 struct dc_state *dsc = dc_states; in dc_state_str() local
467 while (dsc->val != 0xff) { in dc_state_str()
468 if (dsc->val == state) in dc_state_str()
470 dsc++; in dc_state_str()
472 return dsc->name; in dc_state_str()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dsc/
Ddc_dsc.c67 const struct display_stream_compressor *dsc,
343 const struct display_stream_compressor *dsc, in dc_dsc_compute_bandwidth_range() argument
356 get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz); in dc_dsc_compute_bandwidth_range()
373 const struct display_stream_compressor *dsc, in get_dsc_enc_caps() argument
380 if (dsc) { in get_dsc_enc_caps()
381 if (!dsc->ctx->dc->debug.disable_dsc) in get_dsc_enc_caps()
382 dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz); in get_dsc_enc_caps()
383 if (dsc->ctx->dc->debug.native422_support) in get_dsc_enc_caps()
959 const struct display_stream_compressor *dsc, in dc_dsc_compute_config() argument
970 get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz); in dc_dsc_compute_config()
DMakefile6 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
/linux-6.1.9/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsc.yaml4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
24 - const: mediatek,mt8195-disp-dsc
73 compatible = "mediatek,mt8195-disp-dsc";
/linux-6.1.9/drivers/irqchip/
Dirq-partition-percpu.c235 struct irq_domain *partition_get_domain(struct partition_desc *dsc) in partition_get_domain() argument
237 if (dsc) in partition_get_domain()
238 return dsc->domain; in partition_get_domain()

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