1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
5  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
6  *
7  * Author: Rob Clark <robdclark@gmail.com>
8  */
9 
10 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
11 
12 #include <linux/debugfs.h>
13 #include <linux/dma-buf.h>
14 #include <linux/of_irq.h>
15 #include <linux/pm_opp.h>
16 
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_file.h>
19 #include <drm/drm_framebuffer.h>
20 #include <drm/drm_vblank.h>
21 #include <drm/drm_writeback.h>
22 
23 #include "msm_drv.h"
24 #include "msm_mmu.h"
25 #include "msm_gem.h"
26 #include "disp/msm_disp_snapshot.h"
27 
28 #include "dpu_core_irq.h"
29 #include "dpu_crtc.h"
30 #include "dpu_encoder.h"
31 #include "dpu_formats.h"
32 #include "dpu_hw_vbif.h"
33 #include "dpu_kms.h"
34 #include "dpu_plane.h"
35 #include "dpu_vbif.h"
36 #include "dpu_writeback.h"
37 
38 #define CREATE_TRACE_POINTS
39 #include "dpu_trace.h"
40 
41 /*
42  * To enable overall DRM driver logging
43  * # echo 0x2 > /sys/module/drm/parameters/debug
44  *
45  * To enable DRM driver h/w logging
46  * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
47  *
48  * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_)
49  */
50 #define DPU_DEBUGFS_DIR "msm_dpu"
51 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
52 
53 static int dpu_kms_hw_init(struct msm_kms *kms);
54 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
55 
56 #ifdef CONFIG_DEBUG_FS
_dpu_danger_signal_status(struct seq_file * s,bool danger_status)57 static int _dpu_danger_signal_status(struct seq_file *s,
58 		bool danger_status)
59 {
60 	struct dpu_kms *kms = (struct dpu_kms *)s->private;
61 	struct dpu_danger_safe_status status;
62 	int i;
63 
64 	if (!kms->hw_mdp) {
65 		DPU_ERROR("invalid arg(s)\n");
66 		return 0;
67 	}
68 
69 	memset(&status, 0, sizeof(struct dpu_danger_safe_status));
70 
71 	pm_runtime_get_sync(&kms->pdev->dev);
72 	if (danger_status) {
73 		seq_puts(s, "\nDanger signal status:\n");
74 		if (kms->hw_mdp->ops.get_danger_status)
75 			kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
76 					&status);
77 	} else {
78 		seq_puts(s, "\nSafe signal status:\n");
79 		if (kms->hw_mdp->ops.get_safe_status)
80 			kms->hw_mdp->ops.get_safe_status(kms->hw_mdp,
81 					&status);
82 	}
83 	pm_runtime_put_sync(&kms->pdev->dev);
84 
85 	seq_printf(s, "MDP     :  0x%x\n", status.mdp);
86 
87 	for (i = SSPP_VIG0; i < SSPP_MAX; i++)
88 		seq_printf(s, "SSPP%d   :  0x%x  \n", i - SSPP_VIG0,
89 				status.sspp[i]);
90 	seq_puts(s, "\n");
91 
92 	return 0;
93 }
94 
dpu_debugfs_danger_stats_show(struct seq_file * s,void * v)95 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v)
96 {
97 	return _dpu_danger_signal_status(s, true);
98 }
99 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats);
100 
dpu_debugfs_safe_stats_show(struct seq_file * s,void * v)101 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v)
102 {
103 	return _dpu_danger_signal_status(s, false);
104 }
105 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats);
106 
_dpu_plane_danger_read(struct file * file,char __user * buff,size_t count,loff_t * ppos)107 static ssize_t _dpu_plane_danger_read(struct file *file,
108 			char __user *buff, size_t count, loff_t *ppos)
109 {
110 	struct dpu_kms *kms = file->private_data;
111 	int len;
112 	char buf[40];
113 
114 	len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
115 
116 	return simple_read_from_buffer(buff, count, ppos, buf, len);
117 }
118 
_dpu_plane_set_danger_state(struct dpu_kms * kms,bool enable)119 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
120 {
121 	struct drm_plane *plane;
122 
123 	drm_for_each_plane(plane, kms->dev) {
124 		if (plane->fb && plane->state) {
125 			dpu_plane_danger_signal_ctrl(plane, enable);
126 			DPU_DEBUG("plane:%d img:%dx%d ",
127 				plane->base.id, plane->fb->width,
128 				plane->fb->height);
129 			DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
130 				plane->state->src_x >> 16,
131 				plane->state->src_y >> 16,
132 				plane->state->src_w >> 16,
133 				plane->state->src_h >> 16,
134 				plane->state->crtc_x, plane->state->crtc_y,
135 				plane->state->crtc_w, plane->state->crtc_h);
136 		} else {
137 			DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
138 		}
139 	}
140 }
141 
_dpu_plane_danger_write(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)142 static ssize_t _dpu_plane_danger_write(struct file *file,
143 		    const char __user *user_buf, size_t count, loff_t *ppos)
144 {
145 	struct dpu_kms *kms = file->private_data;
146 	int disable_panic;
147 	int ret;
148 
149 	ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
150 	if (ret)
151 		return ret;
152 
153 	if (disable_panic) {
154 		/* Disable panic signal for all active pipes */
155 		DPU_DEBUG("Disabling danger:\n");
156 		_dpu_plane_set_danger_state(kms, false);
157 		kms->has_danger_ctrl = false;
158 	} else {
159 		/* Enable panic signal for all active pipes */
160 		DPU_DEBUG("Enabling danger:\n");
161 		kms->has_danger_ctrl = true;
162 		_dpu_plane_set_danger_state(kms, true);
163 	}
164 
165 	return count;
166 }
167 
168 static const struct file_operations dpu_plane_danger_enable = {
169 	.open = simple_open,
170 	.read = _dpu_plane_danger_read,
171 	.write = _dpu_plane_danger_write,
172 };
173 
dpu_debugfs_danger_init(struct dpu_kms * dpu_kms,struct dentry * parent)174 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
175 		struct dentry *parent)
176 {
177 	struct dentry *entry = debugfs_create_dir("danger", parent);
178 
179 	debugfs_create_file("danger_status", 0600, entry,
180 			dpu_kms, &dpu_debugfs_danger_stats_fops);
181 	debugfs_create_file("safe_status", 0600, entry,
182 			dpu_kms, &dpu_debugfs_safe_stats_fops);
183 	debugfs_create_file("disable_danger", 0600, entry,
184 			dpu_kms, &dpu_plane_danger_enable);
185 
186 }
187 
188 /*
189  * Companion structure for dpu_debugfs_create_regset32.
190  */
191 struct dpu_debugfs_regset32 {
192 	uint32_t offset;
193 	uint32_t blk_len;
194 	struct dpu_kms *dpu_kms;
195 };
196 
_dpu_debugfs_show_regset32(struct seq_file * s,void * data)197 static int _dpu_debugfs_show_regset32(struct seq_file *s, void *data)
198 {
199 	struct dpu_debugfs_regset32 *regset = s->private;
200 	struct dpu_kms *dpu_kms = regset->dpu_kms;
201 	void __iomem *base;
202 	uint32_t i, addr;
203 
204 	if (!dpu_kms->mmio)
205 		return 0;
206 
207 	base = dpu_kms->mmio + regset->offset;
208 
209 	/* insert padding spaces, if needed */
210 	if (regset->offset & 0xF) {
211 		seq_printf(s, "[%x]", regset->offset & ~0xF);
212 		for (i = 0; i < (regset->offset & 0xF); i += 4)
213 			seq_puts(s, "         ");
214 	}
215 
216 	pm_runtime_get_sync(&dpu_kms->pdev->dev);
217 
218 	/* main register output */
219 	for (i = 0; i < regset->blk_len; i += 4) {
220 		addr = regset->offset + i;
221 		if ((addr & 0xF) == 0x0)
222 			seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
223 		seq_printf(s, " %08x", readl_relaxed(base + i));
224 	}
225 	seq_puts(s, "\n");
226 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
227 
228 	return 0;
229 }
230 
dpu_debugfs_open_regset32(struct inode * inode,struct file * file)231 static int dpu_debugfs_open_regset32(struct inode *inode,
232 		struct file *file)
233 {
234 	return single_open(file, _dpu_debugfs_show_regset32, inode->i_private);
235 }
236 
237 static const struct file_operations dpu_fops_regset32 = {
238 	.open =		dpu_debugfs_open_regset32,
239 	.read =		seq_read,
240 	.llseek =	seq_lseek,
241 	.release =	single_release,
242 };
243 
dpu_debugfs_create_regset32(const char * name,umode_t mode,void * parent,uint32_t offset,uint32_t length,struct dpu_kms * dpu_kms)244 void dpu_debugfs_create_regset32(const char *name, umode_t mode,
245 		void *parent,
246 		uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
247 {
248 	struct dpu_debugfs_regset32 *regset;
249 
250 	if (WARN_ON(!name || !dpu_kms || !length))
251 		return;
252 
253 	regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL);
254 	if (!regset)
255 		return;
256 
257 	/* make sure offset is a multiple of 4 */
258 	regset->offset = round_down(offset, 4);
259 	regset->blk_len = length;
260 	regset->dpu_kms = dpu_kms;
261 
262 	debugfs_create_file(name, mode, parent, regset, &dpu_fops_regset32);
263 }
264 
dpu_kms_debugfs_init(struct msm_kms * kms,struct drm_minor * minor)265 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
266 {
267 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
268 	void *p = dpu_hw_util_get_log_mask_ptr();
269 	struct dentry *entry;
270 	struct drm_device *dev;
271 	struct msm_drm_private *priv;
272 	int i;
273 
274 	if (!p)
275 		return -EINVAL;
276 
277 	/* Only create a set of debugfs for the primary node, ignore render nodes */
278 	if (minor->type != DRM_MINOR_PRIMARY)
279 		return 0;
280 
281 	dev = dpu_kms->dev;
282 	priv = dev->dev_private;
283 
284 	entry = debugfs_create_dir("debug", minor->debugfs_root);
285 
286 	debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p);
287 
288 	dpu_debugfs_danger_init(dpu_kms, entry);
289 	dpu_debugfs_vbif_init(dpu_kms, entry);
290 	dpu_debugfs_core_irq_init(dpu_kms, entry);
291 	dpu_debugfs_sspp_init(dpu_kms, entry);
292 
293 	for (i = 0; i < ARRAY_SIZE(priv->dp); i++) {
294 		if (priv->dp[i])
295 			msm_dp_debugfs_init(priv->dp[i], minor);
296 	}
297 
298 	return dpu_core_perf_debugfs_init(dpu_kms, entry);
299 }
300 #endif
301 
302 /* Global/shared object state funcs */
303 
304 /*
305  * This is a helper that returns the private state currently in operation.
306  * Note that this would return the "old_state" if called in the atomic check
307  * path, and the "new_state" after the atomic swap has been done.
308  */
309 struct dpu_global_state *
dpu_kms_get_existing_global_state(struct dpu_kms * dpu_kms)310 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms)
311 {
312 	return to_dpu_global_state(dpu_kms->global_state.state);
313 }
314 
315 /*
316  * This acquires the modeset lock set aside for global state, creates
317  * a new duplicated private object state.
318  */
dpu_kms_get_global_state(struct drm_atomic_state * s)319 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s)
320 {
321 	struct msm_drm_private *priv = s->dev->dev_private;
322 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
323 	struct drm_private_state *priv_state;
324 	int ret;
325 
326 	ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx);
327 	if (ret)
328 		return ERR_PTR(ret);
329 
330 	priv_state = drm_atomic_get_private_obj_state(s,
331 						&dpu_kms->global_state);
332 	if (IS_ERR(priv_state))
333 		return ERR_CAST(priv_state);
334 
335 	return to_dpu_global_state(priv_state);
336 }
337 
338 static struct drm_private_state *
dpu_kms_global_duplicate_state(struct drm_private_obj * obj)339 dpu_kms_global_duplicate_state(struct drm_private_obj *obj)
340 {
341 	struct dpu_global_state *state;
342 
343 	state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
344 	if (!state)
345 		return NULL;
346 
347 	__drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
348 
349 	return &state->base;
350 }
351 
dpu_kms_global_destroy_state(struct drm_private_obj * obj,struct drm_private_state * state)352 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj,
353 				      struct drm_private_state *state)
354 {
355 	struct dpu_global_state *dpu_state = to_dpu_global_state(state);
356 
357 	kfree(dpu_state);
358 }
359 
360 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = {
361 	.atomic_duplicate_state = dpu_kms_global_duplicate_state,
362 	.atomic_destroy_state = dpu_kms_global_destroy_state,
363 };
364 
dpu_kms_global_obj_init(struct dpu_kms * dpu_kms)365 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
366 {
367 	struct dpu_global_state *state;
368 
369 	drm_modeset_lock_init(&dpu_kms->global_state_lock);
370 
371 	state = kzalloc(sizeof(*state), GFP_KERNEL);
372 	if (!state)
373 		return -ENOMEM;
374 
375 	drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state,
376 				    &state->base,
377 				    &dpu_kms_global_state_funcs);
378 	return 0;
379 }
380 
dpu_kms_parse_data_bus_icc_path(struct dpu_kms * dpu_kms)381 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
382 {
383 	struct icc_path *path0;
384 	struct icc_path *path1;
385 	struct drm_device *dev = dpu_kms->dev;
386 	struct device *dpu_dev = dev->dev;
387 
388 	path0 = msm_icc_get(dpu_dev, "mdp0-mem");
389 	path1 = msm_icc_get(dpu_dev, "mdp1-mem");
390 
391 	if (IS_ERR_OR_NULL(path0))
392 		return PTR_ERR_OR_ZERO(path0);
393 
394 	dpu_kms->path[0] = path0;
395 	dpu_kms->num_paths = 1;
396 
397 	if (!IS_ERR_OR_NULL(path1)) {
398 		dpu_kms->path[1] = path1;
399 		dpu_kms->num_paths++;
400 	}
401 	return 0;
402 }
403 
dpu_kms_enable_vblank(struct msm_kms * kms,struct drm_crtc * crtc)404 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
405 {
406 	return dpu_crtc_vblank(crtc, true);
407 }
408 
dpu_kms_disable_vblank(struct msm_kms * kms,struct drm_crtc * crtc)409 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
410 {
411 	dpu_crtc_vblank(crtc, false);
412 }
413 
dpu_kms_enable_commit(struct msm_kms * kms)414 static void dpu_kms_enable_commit(struct msm_kms *kms)
415 {
416 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
417 	pm_runtime_get_sync(&dpu_kms->pdev->dev);
418 }
419 
dpu_kms_disable_commit(struct msm_kms * kms)420 static void dpu_kms_disable_commit(struct msm_kms *kms)
421 {
422 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
423 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
424 }
425 
dpu_kms_vsync_time(struct msm_kms * kms,struct drm_crtc * crtc)426 static ktime_t dpu_kms_vsync_time(struct msm_kms *kms, struct drm_crtc *crtc)
427 {
428 	struct drm_encoder *encoder;
429 
430 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
431 		ktime_t vsync_time;
432 
433 		if (dpu_encoder_vsync_time(encoder, &vsync_time) == 0)
434 			return vsync_time;
435 	}
436 
437 	return ktime_get();
438 }
439 
dpu_kms_prepare_commit(struct msm_kms * kms,struct drm_atomic_state * state)440 static void dpu_kms_prepare_commit(struct msm_kms *kms,
441 		struct drm_atomic_state *state)
442 {
443 	struct drm_crtc *crtc;
444 	struct drm_crtc_state *crtc_state;
445 	struct drm_encoder *encoder;
446 	int i;
447 
448 	if (!kms)
449 		return;
450 
451 	/* Call prepare_commit for all affected encoders */
452 	for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
453 		drm_for_each_encoder_mask(encoder, crtc->dev,
454 					  crtc_state->encoder_mask) {
455 			dpu_encoder_prepare_commit(encoder);
456 		}
457 	}
458 }
459 
dpu_kms_flush_commit(struct msm_kms * kms,unsigned crtc_mask)460 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
461 {
462 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
463 	struct drm_crtc *crtc;
464 
465 	for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) {
466 		if (!crtc->state->active)
467 			continue;
468 
469 		trace_dpu_kms_commit(DRMID(crtc));
470 		dpu_crtc_commit_kickoff(crtc);
471 	}
472 }
473 
dpu_kms_complete_commit(struct msm_kms * kms,unsigned crtc_mask)474 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
475 {
476 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
477 	struct drm_crtc *crtc;
478 
479 	DPU_ATRACE_BEGIN("kms_complete_commit");
480 
481 	for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
482 		dpu_crtc_complete_commit(crtc);
483 
484 	DPU_ATRACE_END("kms_complete_commit");
485 }
486 
dpu_kms_wait_for_commit_done(struct msm_kms * kms,struct drm_crtc * crtc)487 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
488 		struct drm_crtc *crtc)
489 {
490 	struct drm_encoder *encoder;
491 	struct drm_device *dev;
492 	int ret;
493 
494 	if (!kms || !crtc || !crtc->state) {
495 		DPU_ERROR("invalid params\n");
496 		return;
497 	}
498 
499 	dev = crtc->dev;
500 
501 	if (!crtc->state->enable) {
502 		DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
503 		return;
504 	}
505 
506 	if (!crtc->state->active) {
507 		DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
508 		return;
509 	}
510 
511 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
512 		if (encoder->crtc != crtc)
513 			continue;
514 		/*
515 		 * Wait for post-flush if necessary to delay before
516 		 * plane_cleanup. For example, wait for vsync in case of video
517 		 * mode panels. This may be a no-op for command mode panels.
518 		 */
519 		trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
520 		ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
521 		if (ret && ret != -EWOULDBLOCK) {
522 			DPU_ERROR("wait for commit done returned %d\n", ret);
523 			break;
524 		}
525 	}
526 }
527 
dpu_kms_wait_flush(struct msm_kms * kms,unsigned crtc_mask)528 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
529 {
530 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
531 	struct drm_crtc *crtc;
532 
533 	for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
534 		dpu_kms_wait_for_commit_done(kms, crtc);
535 }
536 
_dpu_kms_initialize_dsi(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms)537 static int _dpu_kms_initialize_dsi(struct drm_device *dev,
538 				    struct msm_drm_private *priv,
539 				    struct dpu_kms *dpu_kms)
540 {
541 	struct drm_encoder *encoder = NULL;
542 	struct msm_display_info info;
543 	int i, rc = 0;
544 
545 	if (!(priv->dsi[0] || priv->dsi[1]))
546 		return rc;
547 
548 	/*
549 	 * We support following confiurations:
550 	 * - Single DSI host (dsi0 or dsi1)
551 	 * - Two independent DSI hosts
552 	 * - Bonded DSI0 and DSI1 hosts
553 	 *
554 	 * TODO: Support swapping DSI0 and DSI1 in the bonded setup.
555 	 */
556 	for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
557 		int other = (i + 1) % 2;
558 
559 		if (!priv->dsi[i])
560 			continue;
561 
562 		if (msm_dsi_is_bonded_dsi(priv->dsi[i]) &&
563 		    !msm_dsi_is_master_dsi(priv->dsi[i]))
564 			continue;
565 
566 		encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI);
567 		if (IS_ERR(encoder)) {
568 			DPU_ERROR("encoder init failed for dsi display\n");
569 			return PTR_ERR(encoder);
570 		}
571 
572 		memset(&info, 0, sizeof(info));
573 		info.intf_type = encoder->encoder_type;
574 
575 		rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder);
576 		if (rc) {
577 			DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
578 				i, rc);
579 			break;
580 		}
581 
582 		info.h_tile_instance[info.num_of_h_tiles++] = i;
583 		info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
584 
585 		info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
586 
587 		if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
588 			rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
589 			if (rc) {
590 				DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
591 					other, rc);
592 				break;
593 			}
594 
595 			info.h_tile_instance[info.num_of_h_tiles++] = other;
596 		}
597 
598 		rc = dpu_encoder_setup(dev, encoder, &info);
599 		if (rc)
600 			DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n",
601 				  encoder->base.id, rc);
602 	}
603 
604 	return rc;
605 }
606 
_dpu_kms_initialize_displayport(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms)607 static int _dpu_kms_initialize_displayport(struct drm_device *dev,
608 					    struct msm_drm_private *priv,
609 					    struct dpu_kms *dpu_kms)
610 {
611 	struct drm_encoder *encoder = NULL;
612 	struct msm_display_info info;
613 	int rc;
614 	int i;
615 
616 	for (i = 0; i < ARRAY_SIZE(priv->dp); i++) {
617 		if (!priv->dp[i])
618 			continue;
619 
620 		encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS);
621 		if (IS_ERR(encoder)) {
622 			DPU_ERROR("encoder init failed for dsi display\n");
623 			return PTR_ERR(encoder);
624 		}
625 
626 		memset(&info, 0, sizeof(info));
627 		rc = msm_dp_modeset_init(priv->dp[i], dev, encoder);
628 		if (rc) {
629 			DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
630 			drm_encoder_cleanup(encoder);
631 			return rc;
632 		}
633 
634 		info.num_of_h_tiles = 1;
635 		info.h_tile_instance[0] = i;
636 		info.intf_type = encoder->encoder_type;
637 		rc = dpu_encoder_setup(dev, encoder, &info);
638 		if (rc) {
639 			DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n",
640 				  encoder->base.id, rc);
641 			return rc;
642 		}
643 	}
644 
645 	return 0;
646 }
647 
_dpu_kms_initialize_writeback(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms,const u32 * wb_formats,int n_formats)648 static int _dpu_kms_initialize_writeback(struct drm_device *dev,
649 		struct msm_drm_private *priv, struct dpu_kms *dpu_kms,
650 		const u32 *wb_formats, int n_formats)
651 {
652 	struct drm_encoder *encoder = NULL;
653 	struct msm_display_info info;
654 	int rc;
655 
656 	encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_VIRTUAL);
657 	if (IS_ERR(encoder)) {
658 		DPU_ERROR("encoder init failed for dsi display\n");
659 		return PTR_ERR(encoder);
660 	}
661 
662 	memset(&info, 0, sizeof(info));
663 
664 	rc = dpu_writeback_init(dev, encoder, wb_formats,
665 			n_formats);
666 	if (rc) {
667 		DPU_ERROR("dpu_writeback_init, rc = %d\n", rc);
668 		drm_encoder_cleanup(encoder);
669 		return rc;
670 	}
671 
672 	info.num_of_h_tiles = 1;
673 	/* use only WB idx 2 instance for DPU */
674 	info.h_tile_instance[0] = WB_2;
675 	info.intf_type = encoder->encoder_type;
676 
677 	rc = dpu_encoder_setup(dev, encoder, &info);
678 	if (rc) {
679 		DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n",
680 				  encoder->base.id, rc);
681 		return rc;
682 	}
683 
684 	return 0;
685 }
686 
687 /**
688  * _dpu_kms_setup_displays - create encoders, bridges and connectors
689  *                           for underlying displays
690  * @dev:        Pointer to drm device structure
691  * @priv:       Pointer to private drm device data
692  * @dpu_kms:    Pointer to dpu kms structure
693  * Returns:     Zero on success
694  */
_dpu_kms_setup_displays(struct drm_device * dev,struct msm_drm_private * priv,struct dpu_kms * dpu_kms)695 static int _dpu_kms_setup_displays(struct drm_device *dev,
696 				    struct msm_drm_private *priv,
697 				    struct dpu_kms *dpu_kms)
698 {
699 	int rc = 0;
700 	int i;
701 
702 	rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
703 	if (rc) {
704 		DPU_ERROR("initialize_dsi failed, rc = %d\n", rc);
705 		return rc;
706 	}
707 
708 	rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms);
709 	if (rc) {
710 		DPU_ERROR("initialize_DP failed, rc = %d\n", rc);
711 		return rc;
712 	}
713 
714 	/* Since WB isn't a driver check the catalog before initializing */
715 	if (dpu_kms->catalog->wb_count) {
716 		for (i = 0; i < dpu_kms->catalog->wb_count; i++) {
717 			if (dpu_kms->catalog->wb[i].id == WB_2) {
718 				rc = _dpu_kms_initialize_writeback(dev, priv, dpu_kms,
719 						dpu_kms->catalog->wb[i].format_list,
720 						dpu_kms->catalog->wb[i].num_formats);
721 				if (rc) {
722 					DPU_ERROR("initialize_WB failed, rc = %d\n", rc);
723 					return rc;
724 				}
725 			}
726 		}
727 	}
728 
729 	return rc;
730 }
731 
732 #define MAX_PLANES 20
_dpu_kms_drm_obj_init(struct dpu_kms * dpu_kms)733 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
734 {
735 	struct drm_device *dev;
736 	struct drm_plane *primary_planes[MAX_PLANES], *plane;
737 	struct drm_plane *cursor_planes[MAX_PLANES] = { NULL };
738 	struct drm_crtc *crtc;
739 	struct drm_encoder *encoder;
740 	unsigned int num_encoders;
741 
742 	struct msm_drm_private *priv;
743 	const struct dpu_mdss_cfg *catalog;
744 
745 	int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret;
746 	int max_crtc_count;
747 	dev = dpu_kms->dev;
748 	priv = dev->dev_private;
749 	catalog = dpu_kms->catalog;
750 
751 	/*
752 	 * Create encoder and query display drivers to create
753 	 * bridges and connectors
754 	 */
755 	ret = _dpu_kms_setup_displays(dev, priv, dpu_kms);
756 	if (ret)
757 		return ret;
758 
759 	num_encoders = 0;
760 	drm_for_each_encoder(encoder, dev)
761 		num_encoders++;
762 
763 	max_crtc_count = min(catalog->mixer_count, num_encoders);
764 
765 	/* Create the planes, keeping track of one primary/cursor per crtc */
766 	for (i = 0; i < catalog->sspp_count; i++) {
767 		enum drm_plane_type type;
768 
769 		if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
770 			&& cursor_planes_idx < max_crtc_count)
771 			type = DRM_PLANE_TYPE_CURSOR;
772 		else if (primary_planes_idx < max_crtc_count)
773 			type = DRM_PLANE_TYPE_PRIMARY;
774 		else
775 			type = DRM_PLANE_TYPE_OVERLAY;
776 
777 		DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n",
778 			  type, catalog->sspp[i].features,
779 			  catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR));
780 
781 		plane = dpu_plane_init(dev, catalog->sspp[i].id, type,
782 				       (1UL << max_crtc_count) - 1);
783 		if (IS_ERR(plane)) {
784 			DPU_ERROR("dpu_plane_init failed\n");
785 			ret = PTR_ERR(plane);
786 			return ret;
787 		}
788 
789 		if (type == DRM_PLANE_TYPE_CURSOR)
790 			cursor_planes[cursor_planes_idx++] = plane;
791 		else if (type == DRM_PLANE_TYPE_PRIMARY)
792 			primary_planes[primary_planes_idx++] = plane;
793 	}
794 
795 	max_crtc_count = min(max_crtc_count, primary_planes_idx);
796 
797 	/* Create one CRTC per encoder */
798 	for (i = 0; i < max_crtc_count; i++) {
799 		crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
800 		if (IS_ERR(crtc)) {
801 			ret = PTR_ERR(crtc);
802 			return ret;
803 		}
804 		priv->crtcs[priv->num_crtcs++] = crtc;
805 	}
806 
807 	/* All CRTCs are compatible with all encoders */
808 	drm_for_each_encoder(encoder, dev)
809 		encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
810 
811 	return 0;
812 }
813 
_dpu_kms_hw_destroy(struct dpu_kms * dpu_kms)814 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
815 {
816 	int i;
817 
818 	if (dpu_kms->hw_intr)
819 		dpu_hw_intr_destroy(dpu_kms->hw_intr);
820 	dpu_kms->hw_intr = NULL;
821 
822 	/* safe to call these more than once during shutdown */
823 	_dpu_kms_mmu_destroy(dpu_kms);
824 
825 	if (dpu_kms->catalog) {
826 		for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {
827 			if (dpu_kms->hw_vbif[i]) {
828 				dpu_hw_vbif_destroy(dpu_kms->hw_vbif[i]);
829 				dpu_kms->hw_vbif[i] = NULL;
830 			}
831 		}
832 	}
833 
834 	if (dpu_kms->rm_init)
835 		dpu_rm_destroy(&dpu_kms->rm);
836 	dpu_kms->rm_init = false;
837 
838 	dpu_kms->catalog = NULL;
839 
840 	if (dpu_kms->vbif[VBIF_NRT])
841 		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]);
842 	dpu_kms->vbif[VBIF_NRT] = NULL;
843 
844 	if (dpu_kms->vbif[VBIF_RT])
845 		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
846 	dpu_kms->vbif[VBIF_RT] = NULL;
847 
848 	if (dpu_kms->hw_mdp)
849 		dpu_hw_mdp_destroy(dpu_kms->hw_mdp);
850 	dpu_kms->hw_mdp = NULL;
851 
852 	if (dpu_kms->mmio)
853 		devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio);
854 	dpu_kms->mmio = NULL;
855 }
856 
dpu_kms_destroy(struct msm_kms * kms)857 static void dpu_kms_destroy(struct msm_kms *kms)
858 {
859 	struct dpu_kms *dpu_kms;
860 
861 	if (!kms) {
862 		DPU_ERROR("invalid kms\n");
863 		return;
864 	}
865 
866 	dpu_kms = to_dpu_kms(kms);
867 
868 	_dpu_kms_hw_destroy(dpu_kms);
869 
870 	msm_kms_destroy(&dpu_kms->base);
871 
872 	if (dpu_kms->rpm_enabled)
873 		pm_runtime_disable(&dpu_kms->pdev->dev);
874 }
875 
dpu_irq_postinstall(struct msm_kms * kms)876 static int dpu_irq_postinstall(struct msm_kms *kms)
877 {
878 	struct msm_drm_private *priv;
879 	struct dpu_kms *dpu_kms = to_dpu_kms(kms);
880 	int i;
881 
882 	if (!dpu_kms || !dpu_kms->dev)
883 		return -EINVAL;
884 
885 	priv = dpu_kms->dev->dev_private;
886 	if (!priv)
887 		return -EINVAL;
888 
889 	for (i = 0; i < ARRAY_SIZE(priv->dp); i++)
890 		msm_dp_irq_postinstall(priv->dp[i]);
891 
892 	return 0;
893 }
894 
dpu_kms_mdp_snapshot(struct msm_disp_state * disp_state,struct msm_kms * kms)895 static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms)
896 {
897 	int i;
898 	struct dpu_kms *dpu_kms;
899 	const struct dpu_mdss_cfg *cat;
900 
901 	dpu_kms = to_dpu_kms(kms);
902 
903 	cat = dpu_kms->catalog;
904 
905 	pm_runtime_get_sync(&dpu_kms->pdev->dev);
906 
907 	/* dump CTL sub-blocks HW regs info */
908 	for (i = 0; i < cat->ctl_count; i++)
909 		msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len,
910 				dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i);
911 
912 	/* dump DSPP sub-blocks HW regs info */
913 	for (i = 0; i < cat->dspp_count; i++)
914 		msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len,
915 				dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i);
916 
917 	/* dump INTF sub-blocks HW regs info */
918 	for (i = 0; i < cat->intf_count; i++)
919 		msm_disp_snapshot_add_block(disp_state, cat->intf[i].len,
920 				dpu_kms->mmio + cat->intf[i].base, "intf_%d", i);
921 
922 	/* dump PP sub-blocks HW regs info */
923 	for (i = 0; i < cat->pingpong_count; i++)
924 		msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len,
925 				dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i);
926 
927 	/* dump SSPP sub-blocks HW regs info */
928 	for (i = 0; i < cat->sspp_count; i++)
929 		msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len,
930 				dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i);
931 
932 	/* dump LM sub-blocks HW regs info */
933 	for (i = 0; i < cat->mixer_count; i++)
934 		msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len,
935 				dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i);
936 
937 	/* dump WB sub-blocks HW regs info */
938 	for (i = 0; i < cat->wb_count; i++)
939 		msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
940 				dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
941 
942 	msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
943 			dpu_kms->mmio + cat->mdp[0].base, "top");
944 
945 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
946 }
947 
948 static const struct msm_kms_funcs kms_funcs = {
949 	.hw_init         = dpu_kms_hw_init,
950 	.irq_preinstall  = dpu_core_irq_preinstall,
951 	.irq_postinstall = dpu_irq_postinstall,
952 	.irq_uninstall   = dpu_core_irq_uninstall,
953 	.irq             = dpu_core_irq,
954 	.enable_commit   = dpu_kms_enable_commit,
955 	.disable_commit  = dpu_kms_disable_commit,
956 	.vsync_time      = dpu_kms_vsync_time,
957 	.prepare_commit  = dpu_kms_prepare_commit,
958 	.flush_commit    = dpu_kms_flush_commit,
959 	.wait_flush      = dpu_kms_wait_flush,
960 	.complete_commit = dpu_kms_complete_commit,
961 	.enable_vblank   = dpu_kms_enable_vblank,
962 	.disable_vblank  = dpu_kms_disable_vblank,
963 	.check_modified_format = dpu_format_check_modified_format,
964 	.get_format      = dpu_get_msm_format,
965 	.destroy         = dpu_kms_destroy,
966 	.snapshot        = dpu_kms_mdp_snapshot,
967 #ifdef CONFIG_DEBUG_FS
968 	.debugfs_init    = dpu_kms_debugfs_init,
969 #endif
970 };
971 
_dpu_kms_mmu_destroy(struct dpu_kms * dpu_kms)972 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
973 {
974 	struct msm_mmu *mmu;
975 
976 	if (!dpu_kms->base.aspace)
977 		return;
978 
979 	mmu = dpu_kms->base.aspace->mmu;
980 
981 	mmu->funcs->detach(mmu);
982 	msm_gem_address_space_put(dpu_kms->base.aspace);
983 
984 	dpu_kms->base.aspace = NULL;
985 }
986 
_dpu_kms_mmu_init(struct dpu_kms * dpu_kms)987 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
988 {
989 	struct msm_gem_address_space *aspace;
990 
991 	aspace = msm_kms_init_aspace(dpu_kms->dev);
992 	if (IS_ERR(aspace))
993 		return PTR_ERR(aspace);
994 
995 	dpu_kms->base.aspace = aspace;
996 
997 	return 0;
998 }
999 
dpu_kms_get_clk_rate(struct dpu_kms * dpu_kms,char * clock_name)1000 u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name)
1001 {
1002 	struct clk *clk;
1003 
1004 	clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name);
1005 	if (!clk)
1006 		return -EINVAL;
1007 
1008 	return clk_get_rate(clk);
1009 }
1010 
dpu_kms_hw_init(struct msm_kms * kms)1011 static int dpu_kms_hw_init(struct msm_kms *kms)
1012 {
1013 	struct dpu_kms *dpu_kms;
1014 	struct drm_device *dev;
1015 	int i, rc = -EINVAL;
1016 
1017 	if (!kms) {
1018 		DPU_ERROR("invalid kms\n");
1019 		return rc;
1020 	}
1021 
1022 	dpu_kms = to_dpu_kms(kms);
1023 	dev = dpu_kms->dev;
1024 
1025 	rc = dpu_kms_global_obj_init(dpu_kms);
1026 	if (rc)
1027 		return rc;
1028 
1029 	atomic_set(&dpu_kms->bandwidth_ref, 0);
1030 
1031 	dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp");
1032 	if (IS_ERR(dpu_kms->mmio)) {
1033 		rc = PTR_ERR(dpu_kms->mmio);
1034 		DPU_ERROR("mdp register memory map failed: %d\n", rc);
1035 		dpu_kms->mmio = NULL;
1036 		goto error;
1037 	}
1038 	DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
1039 
1040 	dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif");
1041 	if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
1042 		rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
1043 		DPU_ERROR("vbif register memory map failed: %d\n", rc);
1044 		dpu_kms->vbif[VBIF_RT] = NULL;
1045 		goto error;
1046 	}
1047 	dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(dpu_kms->pdev, "vbif_nrt");
1048 	if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
1049 		dpu_kms->vbif[VBIF_NRT] = NULL;
1050 		DPU_DEBUG("VBIF NRT is not defined");
1051 	}
1052 
1053 	dpu_kms->reg_dma = msm_ioremap_quiet(dpu_kms->pdev, "regdma");
1054 	if (IS_ERR(dpu_kms->reg_dma)) {
1055 		dpu_kms->reg_dma = NULL;
1056 		DPU_DEBUG("REG_DMA is not defined");
1057 	}
1058 
1059 	dpu_kms_parse_data_bus_icc_path(dpu_kms);
1060 
1061 	rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev);
1062 	if (rc < 0)
1063 		goto error;
1064 
1065 	dpu_kms->core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
1066 
1067 	pr_info("dpu hardware revision:0x%x\n", dpu_kms->core_rev);
1068 
1069 	dpu_kms->catalog = dpu_hw_catalog_init(dpu_kms->core_rev);
1070 	if (IS_ERR_OR_NULL(dpu_kms->catalog)) {
1071 		rc = PTR_ERR(dpu_kms->catalog);
1072 		if (!dpu_kms->catalog)
1073 			rc = -EINVAL;
1074 		DPU_ERROR("catalog init failed: %d\n", rc);
1075 		dpu_kms->catalog = NULL;
1076 		goto power_error;
1077 	}
1078 
1079 	/*
1080 	 * Now we need to read the HW catalog and initialize resources such as
1081 	 * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc
1082 	 */
1083 	rc = _dpu_kms_mmu_init(dpu_kms);
1084 	if (rc) {
1085 		DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc);
1086 		goto power_error;
1087 	}
1088 
1089 	rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
1090 	if (rc) {
1091 		DPU_ERROR("rm init failed: %d\n", rc);
1092 		goto power_error;
1093 	}
1094 
1095 	dpu_kms->rm_init = true;
1096 
1097 	dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
1098 					     dpu_kms->catalog);
1099 	if (IS_ERR(dpu_kms->hw_mdp)) {
1100 		rc = PTR_ERR(dpu_kms->hw_mdp);
1101 		DPU_ERROR("failed to get hw_mdp: %d\n", rc);
1102 		dpu_kms->hw_mdp = NULL;
1103 		goto power_error;
1104 	}
1105 
1106 	for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
1107 		u32 vbif_idx = dpu_kms->catalog->vbif[i].id;
1108 
1109 		dpu_kms->hw_vbif[vbif_idx] = dpu_hw_vbif_init(vbif_idx,
1110 				dpu_kms->vbif[vbif_idx], dpu_kms->catalog);
1111 		if (IS_ERR(dpu_kms->hw_vbif[vbif_idx])) {
1112 			rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]);
1113 			DPU_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
1114 			dpu_kms->hw_vbif[vbif_idx] = NULL;
1115 			goto power_error;
1116 		}
1117 	}
1118 
1119 	rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog,
1120 			msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, "core"));
1121 	if (rc) {
1122 		DPU_ERROR("failed to init perf %d\n", rc);
1123 		goto perf_err;
1124 	}
1125 
1126 	dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog);
1127 	if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) {
1128 		rc = PTR_ERR(dpu_kms->hw_intr);
1129 		DPU_ERROR("hw_intr init failed: %d\n", rc);
1130 		dpu_kms->hw_intr = NULL;
1131 		goto hw_intr_init_err;
1132 	}
1133 
1134 	dev->mode_config.min_width = 0;
1135 	dev->mode_config.min_height = 0;
1136 
1137 	/*
1138 	 * max crtc width is equal to the max mixer width * 2 and max height is
1139 	 * is 4K
1140 	 */
1141 	dev->mode_config.max_width =
1142 			dpu_kms->catalog->caps->max_mixer_width * 2;
1143 	dev->mode_config.max_height = 4096;
1144 
1145 	dev->max_vblank_count = 0xffffffff;
1146 	/* Disable vblank irqs aggressively for power-saving */
1147 	dev->vblank_disable_immediate = true;
1148 
1149 	/*
1150 	 * _dpu_kms_drm_obj_init should create the DRM related objects
1151 	 * i.e. CRTCs, planes, encoders, connectors and so forth
1152 	 */
1153 	rc = _dpu_kms_drm_obj_init(dpu_kms);
1154 	if (rc) {
1155 		DPU_ERROR("modeset init failed: %d\n", rc);
1156 		goto drm_obj_init_err;
1157 	}
1158 
1159 	dpu_vbif_init_memtypes(dpu_kms);
1160 
1161 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
1162 
1163 	return 0;
1164 
1165 drm_obj_init_err:
1166 	dpu_core_perf_destroy(&dpu_kms->perf);
1167 hw_intr_init_err:
1168 perf_err:
1169 power_error:
1170 	pm_runtime_put_sync(&dpu_kms->pdev->dev);
1171 error:
1172 	_dpu_kms_hw_destroy(dpu_kms);
1173 
1174 	return rc;
1175 }
1176 
dpu_kms_init(struct drm_device * ddev)1177 static int dpu_kms_init(struct drm_device *ddev)
1178 {
1179 	struct msm_drm_private *priv = ddev->dev_private;
1180 	struct device *dev = ddev->dev;
1181 	struct platform_device *pdev = to_platform_device(dev);
1182 	struct dpu_kms *dpu_kms;
1183 	int irq;
1184 	struct dev_pm_opp *opp;
1185 	int ret = 0;
1186 	unsigned long max_freq = ULONG_MAX;
1187 
1188 	dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL);
1189 	if (!dpu_kms)
1190 		return -ENOMEM;
1191 
1192 	ret = devm_pm_opp_set_clkname(dev, "core");
1193 	if (ret)
1194 		return ret;
1195 	/* OPP table is optional */
1196 	ret = devm_pm_opp_of_add_table(dev);
1197 	if (ret && ret != -ENODEV) {
1198 		dev_err(dev, "invalid OPP table in device tree\n");
1199 		return ret;
1200 	}
1201 
1202 	ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks);
1203 	if (ret < 0) {
1204 		DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
1205 		return ret;
1206 	}
1207 	dpu_kms->num_clocks = ret;
1208 
1209 	opp = dev_pm_opp_find_freq_floor(dev, &max_freq);
1210 	if (!IS_ERR(opp))
1211 		dev_pm_opp_put(opp);
1212 
1213 	dev_pm_opp_set_rate(dev, max_freq);
1214 
1215 	ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
1216 	if (ret) {
1217 		DPU_ERROR("failed to init kms, ret=%d\n", ret);
1218 		return ret;
1219 	}
1220 	dpu_kms->dev = ddev;
1221 	dpu_kms->pdev = pdev;
1222 
1223 	pm_runtime_enable(&pdev->dev);
1224 	dpu_kms->rpm_enabled = true;
1225 
1226 	priv->kms = &dpu_kms->base;
1227 
1228 	irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0);
1229 	if (!irq) {
1230 		DPU_ERROR("failed to get irq\n");
1231 		return -EINVAL;
1232 	}
1233 	dpu_kms->base.irq = irq;
1234 
1235 	return 0;
1236 }
1237 
dpu_dev_probe(struct platform_device * pdev)1238 static int dpu_dev_probe(struct platform_device *pdev)
1239 {
1240 	return msm_drv_probe(&pdev->dev, dpu_kms_init);
1241 }
1242 
dpu_dev_remove(struct platform_device * pdev)1243 static int dpu_dev_remove(struct platform_device *pdev)
1244 {
1245 	component_master_del(&pdev->dev, &msm_drm_ops);
1246 
1247 	return 0;
1248 }
1249 
dpu_runtime_suspend(struct device * dev)1250 static int __maybe_unused dpu_runtime_suspend(struct device *dev)
1251 {
1252 	int i;
1253 	struct platform_device *pdev = to_platform_device(dev);
1254 	struct msm_drm_private *priv = platform_get_drvdata(pdev);
1255 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1256 
1257 	/* Drop the performance state vote */
1258 	dev_pm_opp_set_rate(dev, 0);
1259 	clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks);
1260 
1261 	for (i = 0; i < dpu_kms->num_paths; i++)
1262 		icc_set_bw(dpu_kms->path[i], 0, 0);
1263 
1264 	return 0;
1265 }
1266 
dpu_runtime_resume(struct device * dev)1267 static int __maybe_unused dpu_runtime_resume(struct device *dev)
1268 {
1269 	int rc = -1;
1270 	struct platform_device *pdev = to_platform_device(dev);
1271 	struct msm_drm_private *priv = platform_get_drvdata(pdev);
1272 	struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1273 	struct drm_encoder *encoder;
1274 	struct drm_device *ddev;
1275 
1276 	ddev = dpu_kms->dev;
1277 
1278 	rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks);
1279 	if (rc) {
1280 		DPU_ERROR("clock enable failed rc:%d\n", rc);
1281 		return rc;
1282 	}
1283 
1284 	dpu_vbif_init_memtypes(dpu_kms);
1285 
1286 	drm_for_each_encoder(encoder, ddev)
1287 		dpu_encoder_virt_runtime_resume(encoder);
1288 
1289 	return rc;
1290 }
1291 
1292 static const struct dev_pm_ops dpu_pm_ops = {
1293 	SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
1294 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1295 				pm_runtime_force_resume)
1296 	.prepare = msm_pm_prepare,
1297 	.complete = msm_pm_complete,
1298 };
1299 
1300 static const struct of_device_id dpu_dt_match[] = {
1301 	{ .compatible = "qcom,msm8998-dpu", },
1302 	{ .compatible = "qcom,qcm2290-dpu", },
1303 	{ .compatible = "qcom,sdm845-dpu", },
1304 	{ .compatible = "qcom,sc7180-dpu", },
1305 	{ .compatible = "qcom,sc7280-dpu", },
1306 	{ .compatible = "qcom,sc8180x-dpu", },
1307 	{ .compatible = "qcom,sm8150-dpu", },
1308 	{ .compatible = "qcom,sm8250-dpu", },
1309 	{}
1310 };
1311 MODULE_DEVICE_TABLE(of, dpu_dt_match);
1312 
1313 static struct platform_driver dpu_driver = {
1314 	.probe = dpu_dev_probe,
1315 	.remove = dpu_dev_remove,
1316 	.shutdown = msm_drv_shutdown,
1317 	.driver = {
1318 		.name = "msm_dpu",
1319 		.of_match_table = dpu_dt_match,
1320 		.pm = &dpu_pm_ops,
1321 	},
1322 };
1323 
msm_dpu_register(void)1324 void __init msm_dpu_register(void)
1325 {
1326 	platform_driver_register(&dpu_driver);
1327 }
1328 
msm_dpu_unregister(void)1329 void __exit msm_dpu_unregister(void)
1330 {
1331 	platform_driver_unregister(&dpu_driver);
1332 }
1333