Searched refs:divsel (Results 1 – 3 of 3) sorted by relevance
| /linux-6.1.9/drivers/gpu/drm/i915/display/ |
| D | intel_pch_refclk.c | 128 u32 divsel, phaseinc, auxdiv, phasedir, desired_divisor; member
158 p->divsel = (p->desired_divisor / p->iclk_pi_range) - 2; in lpt_compute_iclkip()
165 if (p->divsel <= 0x7f) in lpt_compute_iclkip()
194 drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(p.divsel) & in lpt_program_iclkip()
201 clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc); in lpt_program_iclkip()
208 temp |= SBI_SSCDIVINTPHASE_DIVSEL(p.divsel); in lpt_program_iclkip()
253 p.divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> in lpt_get_iclkip()
264 p.desired_divisor = (p.divsel + 2) * p.iclk_pi_range + p.phaseinc; in lpt_get_iclkip()
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| /linux-6.1.9/drivers/mfd/ |
| D | db8500-prcmu.c | 504 u32 divsel; member
511 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
516 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
1349 val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) << in request_dsiclk()
1503 u32 divsel; in dsiclk_rate() local
1506 divsel = readl(PRCM_DSI_PLLOUT_SEL); in dsiclk_rate()
1507 divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift); in dsiclk_rate()
1509 if (divsel == PRCM_DSI_PLLOUT_SEL_OFF) in dsiclk_rate()
1510 divsel = dsiclk[n].divsel; in dsiclk_rate()
1512 dsiclk[n].divsel = divsel; in dsiclk_rate()
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| /linux-6.1.9/sound/soc/codecs/ |
| D | wm9713.c | 741 u32 divsel:1; member
764 pll_div->divsel = 1; in pll_factors()
773 pll_div->divsel = 0; in pll_factors()
834 (pll_div.divsel << 9) | (pll_div.divctl << 8); in wm9713_set_pll()
839 (pll_div.divsel << 9) | (pll_div.divctl << 8); in wm9713_set_pll()
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