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Searched refs:divp_shift (Results 1 – 6 of 6) sorted by relevance

/linux-6.1.9/drivers/clk/tegra/
Dclk-tegra124.c148 .divp_shift = 20,
244 .divp_shift = 20,
318 .divp_shift = 20,
408 .divp_shift = 20,
466 .divp_shift = 24,
505 .divp_shift = 16,
533 .divp_shift = 20,
598 .divp_shift = 20,
715 .divp_shift = 20,
Dclk-tegra114.c144 .divp_shift = 20,
206 .divp_shift = 20,
279 .divp_shift = 20,
326 .divp_shift = 20,
452 .divp_shift = 20,
550 .divp_shift = 24,
579 .divp_shift = 16,
Dclk-tegra210.c1406 #define divp_shift(p) ((p)->params->div_nmp->divp_shift) macro
1410 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
1571 .divp_shift = 20,
1693 .divp_shift = 20,
1739 .divp_shift = 20,
1808 .divp_shift = 19,
1887 .divp_shift = 20,
1960 .divp_shift = 24,
1997 .divp_shift = 16,
2030 .divp_shift = 20,
[all …]
Dclk-pll.c254 #define divp_shift(p) (p)->params->div_nmp->divp_shift macro
258 #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p))
272 .divp_shift = PLL_BASE_DIVP_SHIFT,
684 (cfg->p << divp_shift(pll)); in _update_pll_mnp()
715 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); in _get_pll_mnp()
992 val |= sel.p << divp_shift(pll); in clk_plle_enable()
1024 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); in clk_plle_recalc_rate()
1947 .divp_shift = PLLE_BASE_DIVP_SHIFT,
Dclk.h203 u8 divp_shift; member
Dclk-tegra30.c377 .divp_shift = 20,