Searched refs:div_val (Results 1 – 6 of 6) sorted by relevance
| /linux-6.1.9/drivers/clk/mmp/ |
| D | clk-mix.c | 131 static int _set_rate(struct mmp_clk_mix *mix, u32 mux_val, u32 div_val, in _set_rate() argument
156 mux_div |= MMP_CLK_BITS_SET_VAL(div_val, width, shift); in _set_rate()
277 u32 div_val, mux_val; in mmp_clk_mix_set_rate_and_parent() local
280 div_val = _get_div_val(mix, div); in mmp_clk_mix_set_rate_and_parent()
283 return _set_rate(mix, mux_val, div_val, 1, 1); in mmp_clk_mix_set_rate_and_parent()
350 u32 div_val, mux_val; in mmp_clk_set_parent() local
361 div_val = _get_div_val(mix, item->divisor); in mmp_clk_set_parent()
367 div_val = 0; in mmp_clk_set_parent()
370 return _set_rate(mix, mux_val, div_val, 1, div_val ? 1 : 0); in mmp_clk_set_parent()
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| /linux-6.1.9/drivers/clk/x86/ |
| D | clk-cgu.h | 192 unsigned int div_val; member
240 .div_val = _v, \
278 .div_val = _v, \
298 .div_val = _v, \
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| D | clk-cgu.c | 32 list->div_width, list->div_val); in lgm_clk_register_fixed()
256 lgm_set_clk_val(div->membase, reg, shift, width, list->div_val); in lgm_clk_register_divider()
279 list->div_width, list->div_val); in lgm_clk_register_fixed_factor()
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| /linux-6.1.9/drivers/media/cec/platform/s5p/ |
| D | exynos_hdmi_cecctrl.c | 25 u32 div_ratio, div_val; in s5p_cec_set_divider() local
42 div_val = CEC_DIV_RATIO * 0.00005 - 1; in s5p_cec_set_divider()
47 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider()
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| /linux-6.1.9/drivers/clk/ |
| D | clk-k210.c | 753 u32 reg, div_val; in k210_clk_get_rate() local
759 div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0); in k210_clk_get_rate()
763 return parent_rate / (div_val + 1); in k210_clk_get_rate()
765 return parent_rate / ((div_val + 1) * 2); in k210_clk_get_rate()
767 return parent_rate / (2UL << div_val); in k210_clk_get_rate()
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| /linux-6.1.9/drivers/clk/imx/ |
| D | clk-pll14xx.c | 289 u32 tmp, div_val; in clk_pll1416x_set_rate() local
322 div_val = FIELD_PREP(MDIV_MASK, rate->mdiv) | FIELD_PREP(PDIV_MASK, rate->pdiv) | in clk_pll1416x_set_rate()
324 writel_relaxed(div_val, pll->base + DIV_CTL0); in clk_pll1416x_set_rate()
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