| /linux-6.1.9/drivers/clk/socfpga/ |
| D | clk-periph.c | 26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
61 u32 div_reg[3]; in __socfpga_periph_init() local
71 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
73 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_periph_init()
74 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
75 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
77 periph_clk->div_reg = NULL; in __socfpga_periph_init()
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| D | clk-periph-a10.c | 28 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
29 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
71 u32 div_reg[3]; in __socfpga_periph_init() local
81 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
83 periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_periph_init()
84 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
85 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
87 periph_clk->div_reg = NULL; in __socfpga_periph_init()
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| D | clk-gate-a10.c | 29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
98 u32 div_reg[3]; in __socfpga_gate_init() local
130 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
132 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_gate_init()
133 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
134 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
136 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
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| D | clk-gate.c | 98 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
99 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
102 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()
174 u32 div_reg[3]; in socfpga_gate_init() local
214 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in socfpga_gate_init()
216 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in socfpga_gate_init()
217 socfpga_clk->shift = div_reg[1]; in socfpga_gate_init()
218 socfpga_clk->width = div_reg[2]; in socfpga_gate_init()
220 socfpga_clk->div_reg = NULL; in socfpga_gate_init()
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| D | clk-gate-s10.c | 29 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
43 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_dbg_clk_recalc_rate()
147 if (clks->div_reg) in s10_register_gate()
148 socfpga_clk->div_reg = regbase + clks->div_reg; in s10_register_gate()
150 socfpga_clk->div_reg = NULL; in s10_register_gate()
205 if (clks->div_reg) in agilex_register_gate()
206 socfpga_clk->div_reg = regbase + clks->div_reg; in agilex_register_gate()
208 socfpga_clk->div_reg = NULL; in agilex_register_gate()
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| D | clk.h | 47 void __iomem *div_reg; member
60 void __iomem *div_reg; member
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| D | stratix10-clk.h | 66 unsigned long div_reg; member
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| /linux-6.1.9/drivers/clk/bcm/ |
| D | clk-bcm2835.c | 492 u32 div_reg; member
1032 div = cprman_read(cprman, data->div_reg); in bcm2835_clock_get_rate()
1123 cprman_write(cprman, data->div_reg, div); in bcm2835_clock_set_rate()
1945 .div_reg = CM_OTPDIV,
1957 .div_reg = CM_TIMERDIV,
1968 .div_reg = CM_TSENSDIV,
1975 .div_reg = CM_TECDIV,
1984 .div_reg = CM_H264DIV,
1992 .div_reg = CM_ISPDIV,
2005 .div_reg = CM_SDCDIV,
[all …]
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| /linux-6.1.9/sound/soc/jz4740/ |
| D | jz4740-i2s.c | 279 uint32_t ctrl, div_reg; in jz4740_i2s_hw_params() local
284 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV); in jz4740_i2s_hw_params()
306 div_reg &= ~I2SDIV_DV_MASK; in jz4740_i2s_hw_params()
307 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; in jz4740_i2s_hw_params()
313 div_reg &= ~I2SDIV_IDV_MASK; in jz4740_i2s_hw_params()
314 div_reg |= (div - 1) << I2SDIV_IDV_SHIFT; in jz4740_i2s_hw_params()
316 div_reg &= ~I2SDIV_DV_MASK; in jz4740_i2s_hw_params()
317 div_reg |= (div - 1) << I2SDIV_DV_SHIFT; in jz4740_i2s_hw_params()
322 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg); in jz4740_i2s_hw_params()
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| /linux-6.1.9/sound/soc/mediatek/mt8192/ |
| D | mt8192-afe-clk.c | 414 int div_reg; member
429 .div_reg = CLK_AUDDIV_2,
442 .div_reg = CLK_AUDDIV_2,
455 .div_reg = CLK_AUDDIV_2,
468 .div_reg = CLK_AUDDIV_2,
481 .div_reg = CLK_AUDDIV_3,
494 .div_reg = CLK_AUDDIV_2,
504 .div_reg = CLK_AUDDIV_3,
517 .div_reg = CLK_AUDDIV_3,
530 .div_reg = CLK_AUDDIV_4,
[all …]
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| /linux-6.1.9/drivers/clk/ |
| D | clk-vt8500.c | 22 void __iomem *div_reg; member
118 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
189 writel(divisor, cdev->div_reg); in vt8500_dclk_set_rate()
225 u32 en_reg, div_reg; in vtwm_device_clk_init() local
255 rc = of_property_read_u32(node, "divisor-reg", &div_reg); in vtwm_device_clk_init()
257 dev_clk->div_reg = pmc_base + div_reg; in vtwm_device_clk_init()
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| D | clk-en7523.c | 39 u16 div_reg; member
107 .div_reg = REG_SPI_CLK_DIV_SEL,
180 reg = desc->div_reg ? desc->div_reg : desc->base_reg; in en7523_get_div()
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| D | clk-k210.c | 35 u8 div_reg; member
55 .div_reg = (_reg), \
755 if (!cfg->div_reg) in k210_clk_get_rate()
758 reg = readl(ksc->regs + cfg->div_reg); in k210_clk_get_rate()
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| D | clk-bm1880.c | 116 u32 div_reg; member
151 .div_reg = _div_reg, \
811 div_hws->div.reg = clks->div_reg; in bm1880_clk_register_composite()
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| /linux-6.1.9/drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 226 u32 div_reg; member
242 void __iomem *div_reg; member
372 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
374 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
432 mclk->div_reg = base + mmc_clk->div_reg; in hisi_register_clk_mmc()
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| /linux-6.1.9/drivers/clk/mediatek/ |
| D | clk-mtk.h | 164 u32 div_reg; member
175 .div_reg = _reg, \
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| D | clk-mt8167.c | 662 .div_reg = _reg, \
692 .div_reg = _reg, \
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| D | clk-mtk.c | 398 mcd->flags, base + mcd->div_reg, mcd->div_shift, in mtk_clk_register_dividers()
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| D | clk-mt8516.c | 472 .div_reg = _reg, \
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| D | clk-mt8365.c | 554 .div_reg = _reg, \
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| /linux-6.1.9/drivers/clk/samsung/ |
| D | clk-cpu.c | 69 static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) in wait_until_divider_stable() argument
74 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
78 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
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| /linux-6.1.9/drivers/gpio/ |
| D | gpio-rockchip.c | 202 unsigned long flags, div_reg, freq, max_debounce; in rockchip_gpio_set_debounce() local
215 div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; in rockchip_gpio_set_debounce()
228 if (cur_div_reg < div_reg) in rockchip_gpio_set_debounce()
229 writel(div_reg, bank->reg_base + in rockchip_gpio_set_debounce()
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| /linux-6.1.9/drivers/clk/ingenic/ |
| D | cgu.c | 388 u32 div_reg, div; in ingenic_clk_recalc_rate() local
395 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
396 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
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| /linux-6.1.9/drivers/net/ethernet/netronome/nfp/bpf/ |
| D | jit.c | 2406 static int div_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) in div_reg() function
3459 [BPF_ALU | BPF_DIV | BPF_X] = div_reg,
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