Searched refs:deferred_reg_writes (Results 1 – 4 of 4) sorted by relevance
488 if (dpp_base->deferred_reg_writes.bits.disable_dscl) { in dpp3_deferred_update()490 dpp_base->deferred_reg_writes.bits.disable_dscl = false; in dpp3_deferred_update()493 if (dpp_base->deferred_reg_writes.bits.disable_gamcor) { in dpp3_deferred_update()499 dpp_base->deferred_reg_writes.bits.disable_gamcor = false; in dpp3_deferred_update()502 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) { in dpp3_deferred_update()508 dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false; in dpp3_deferred_update()511 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) { in dpp3_deferred_update()517 dpp_base->deferred_reg_writes.bits.disable_3dlut = false; in dpp3_deferred_update()520 if (dpp_base->deferred_reg_writes.bits.disable_shaper) { in dpp3_deferred_update()526 dpp_base->deferred_reg_writes.bits.disable_shaper = false; in dpp3_deferred_update()[all …]
141 dpp_base->deferred_reg_writes.bits.disable_gamcor = true; in dpp3_power_on_gamcor_lut()
58 union defer_reg_writes deferred_reg_writes; member
173 dpp->base.deferred_reg_writes.bits.disable_dscl = true; in dpp1_power_on_dscl()