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Searched refs:ddc (Results 1 – 25 of 302) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/mediatek/
Dmtk_hdmi_ddc.c62 static inline void sif_set_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_set_bit() argument
65 writel(readl(ddc->regs + offset) | val, ddc->regs + offset); in sif_set_bit()
68 static inline void sif_clr_bit(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_clr_bit() argument
71 writel(readl(ddc->regs + offset) & ~val, ddc->regs + offset); in sif_clr_bit()
74 static inline bool sif_bit_is_set(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_bit_is_set() argument
77 return (readl(ddc->regs + offset) & val) == val; in sif_bit_is_set()
80 static inline void sif_write_mask(struct mtk_hdmi_ddc *ddc, unsigned int offset, in sif_write_mask() argument
86 tmp = readl(ddc->regs + offset); in sif_write_mask()
89 writel(tmp, ddc->regs + offset); in sif_write_mask()
92 static inline unsigned int sif_read_mask(struct mtk_hdmi_ddc *ddc, in sif_read_mask() argument
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/
Dgpio_service.c466 struct ddc *dal_gpio_create_ddc( in dal_gpio_create_ddc()
474 struct ddc *ddc; in dal_gpio_create_ddc() local
479 ddc = kzalloc(sizeof(struct ddc), GFP_KERNEL); in dal_gpio_create_ddc()
481 if (!ddc) { in dal_gpio_create_ddc()
486 ddc->pin_data = dal_gpio_create( in dal_gpio_create_ddc()
489 if (!ddc->pin_data) { in dal_gpio_create_ddc()
494 ddc->pin_clock = dal_gpio_create( in dal_gpio_create_ddc()
497 if (!ddc->pin_clock) { in dal_gpio_create_ddc()
502 ddc->hw_info = *info; in dal_gpio_create_ddc()
504 ddc->ctx = service->ctx; in dal_gpio_create_ddc()
[all …]
Dhw_ddc.c39 ddc->shifts->field_name, ddc->masks->field_name
42 ddc->base.base.ctx
44 (ddc->regs->reg)
70 struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr); in set_config() local
77 hw_gpio = &ddc->base; in set_config()
89 switch (config_data->config.ddc.type) { in set_config()
139 if (config_data->config.ddc.data_en_bit_present || in set_config()
140 config_data->config.ddc.clock_en_bit_present) in set_config()
152 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { in set_config()
156 if (ddc->regs->phy_aux_cntl != 0) { in set_config()
[all …]
Dgpio_base.c69 if (!gpio->hw_container.ddc) { in dal_gpio_open_ex()
238 return gpio->hw_container.ddc; in dal_gpio_get_ddc()
290 gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); in dal_gpio_create()
293 gpio->service->factory.funcs->init_ddc_data(&gpio->hw_container.ddc, service->ctx, id, en); in dal_gpio_create()
324 kfree((*gpio)->hw_container.ddc); in dal_gpio_destroy()
325 (*gpio)->hw_container.ddc = NULL; in dal_gpio_destroy()
329 kfree((*gpio)->hw_container.ddc); in dal_gpio_destroy()
330 (*gpio)->hw_container.ddc = NULL; in dal_gpio_destroy()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_ddc.c242 static void ddc_service_destruct(struct ddc_service *ddc) in ddc_service_destruct() argument
244 if (ddc->ddc_pin) in ddc_service_destruct()
245 dal_gpio_destroy_ddc(&ddc->ddc_pin); in ddc_service_destruct()
248 void dal_ddc_service_destroy(struct ddc_service **ddc) in dal_ddc_service_destroy() argument
250 if (!ddc || !*ddc) { in dal_ddc_service_destroy()
254 ddc_service_destruct(*ddc); in dal_ddc_service_destroy()
255 kfree(*ddc); in dal_ddc_service_destroy()
256 *ddc = NULL; in dal_ddc_service_destroy()
259 enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc) in dal_ddc_service_get_type() argument
265 struct ddc_service *ddc, in dal_ddc_service_set_transaction_type() argument
[all …]
/linux-6.1.9/drivers/gpu/drm/sun4i/
Dsun4i_hdmi_ddc_clk.c65 struct sun4i_ddc *ddc = hw_to_ddc(hw); in sun4i_ddc_round_rate() local
67 return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div, in sun4i_ddc_round_rate()
68 ddc->m_offset, NULL, NULL); in sun4i_ddc_round_rate()
74 struct sun4i_ddc *ddc = hw_to_ddc(hw); in sun4i_ddc_recalc_rate() local
78 regmap_field_read(ddc->reg, &reg); in sun4i_ddc_recalc_rate()
82 return (((parent_rate / ddc->pre_div) / 10) >> n) / in sun4i_ddc_recalc_rate()
83 (m + ddc->m_offset); in sun4i_ddc_recalc_rate()
89 struct sun4i_ddc *ddc = hw_to_ddc(hw); in sun4i_ddc_set_rate() local
92 sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div, in sun4i_ddc_set_rate()
93 ddc->m_offset, &div_m, &div_n); in sun4i_ddc_set_rate()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce/
Ddce_i2c_sw.c40 struct ddc *ddc, in read_bit_from_ddc() argument
46 dal_gpio_get_value(ddc->pin_data, &value); in read_bit_from_ddc()
48 dal_gpio_get_value(ddc->pin_clock, &value); in read_bit_from_ddc()
54 struct ddc *ddc, in write_bit_to_ddc() argument
61 dal_gpio_set_value(ddc->pin_data, value); in write_bit_to_ddc()
63 dal_gpio_set_value(ddc->pin_clock, value); in write_bit_to_ddc()
70 dal_ddc_close(dce_i2c_sw->ddc); in release_engine_dce_sw()
71 dce_i2c_sw->ddc = NULL; in release_engine_dce_sw()
76 struct ddc *ddc, in wait_for_scl_high_sw() argument
85 if (read_bit_from_ddc(ddc, SCL)) in wait_for_scl_high_sw()
[all …]
Ddce_i2c.c30 struct ddc_service *ddc, in dce_i2c_oem_device_present() argument
34 struct dc *dc = ddc->ctx->dc; in dce_i2c_oem_device_present()
56 struct ddc *ddc, in dce_i2c_submit_command() argument
62 if (!ddc) { in dce_i2c_submit_command()
72 dce_i2c_hw = acquire_i2c_hw_engine(pool, ddc); in dce_i2c_submit_command()
75 return dce_i2c_submit_command_hw(pool, ddc, cmd, dce_i2c_hw); in dce_i2c_submit_command()
77 dce_i2c_sw.ctx = ddc->ctx; in dce_i2c_submit_command()
78 if (dce_i2c_engine_acquire_sw(&dce_i2c_sw, ddc)) { in dce_i2c_submit_command()
79 return dce_i2c_submit_command_sw(pool, ddc, cmd, &dce_i2c_sw); in dce_i2c_submit_command()
Ddce_aux.c83 dal_ddc_close(engine->ddc); in release_engine()
85 engine->ddc = NULL; in release_engine()
277 EVENT_LOG_AUX_REQ(engine->ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE, in submit_channel_request()
400 struct ddc *ddc) in acquire() argument
407 result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE, in acquire()
414 engine->ddc = ddc; in acquire()
419 engine->ddc = ddc; in acquire()
434 static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc, in dce_aux_configure_timeout() argument
442 struct ddc *ddc_pin = ddc->ddc_pin; in dce_aux_configure_timeout()
443 struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]; in dce_aux_configure_timeout()
[all …]
Ddce_i2c_sw.h36 struct ddc *ddc; member
48 struct ddc *ddc,
54 struct ddc *ddc_handle);
Ddce_i2c.h35 struct ddc_service *ddc,
41 struct ddc *ddc,
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/
Ddc_link_ddc.h78 void dal_ddc_service_destroy(struct ddc_service **ddc);
80 enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc);
83 struct ddc_service *ddc,
86 bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc);
89 struct ddc_service *ddc,
93 struct ddc_service *ddc,
100 bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
103 int dc_link_aux_transfer_raw(struct ddc_service *ddc,
107 bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
110 bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc,
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/include/
Dgpio_service_interface.h71 struct ddc *dal_gpio_create_ddc(
78 struct ddc **ddc);
103 struct ddc *ddc,
108 struct ddc *ddc,
112 const struct ddc *ddc);
115 struct ddc *ddc,
119 struct ddc *ddc);
/linux-6.1.9/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,hdmi-ddc.yaml4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
19 - mediatek,mt7623-hdmi-ddc
20 - mediatek,mt8167-hdmi-ddc
21 - mediatek,mt8173-hdmi-ddc
34 - const: ddc-i2c
51 compatible = "mediatek,mt8173-hdmi-ddc";
55 clock-names = "ddc-i2c";
/linux-6.1.9/drivers/gpu/drm/tegra/
Doutput.c35 else if (output->ddc) in tegra_output_connector_get_modes()
36 edid = drm_get_edid(connector, output->ddc); in tegra_output_connector_get_modes()
96 struct device_node *ddc, *panel; in tegra_output_probe() local
125 ddc = of_parse_phandle(output->of_node, "nvidia,ddc-i2c-bus", 0); in tegra_output_probe()
126 if (ddc) { in tegra_output_probe()
127 output->ddc = of_get_i2c_adapter_by_node(ddc); in tegra_output_probe()
128 of_node_put(ddc); in tegra_output_probe()
130 if (!output->ddc) { in tegra_output_probe()
186 if (output->ddc) in tegra_output_remove()
187 i2c_put_adapter(output->ddc); in tegra_output_remove()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/dce110/
Dhw_factory_dce110.c116 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
120 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
121 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
124 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
132 ddc->shifts = &ddc_shift; in define_ddc_registers()
133 ddc->masks = &ddc_mask; in define_ddc_registers()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/dce60/
Dhw_factory_dce60.c120 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
124 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
128 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
129 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
136 ddc->shifts = &ddc_shift; in define_ddc_registers()
137 ddc->masks = &ddc_mask; in define_ddc_registers()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/dce80/
Dhw_factory_dce80.c120 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
124 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
125 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
128 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
129 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
136 ddc->shifts = &ddc_shift; in define_ddc_registers()
137 ddc->masks = &ddc_mask; in define_ddc_registers()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/dce120/
Dhw_factory_dce120.c133 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
137 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
138 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
141 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
142 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
149 ddc->shifts = &ddc_shift; in define_ddc_registers()
150 ddc->masks = &ddc_mask; in define_ddc_registers()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
Dhw_factory_dcn10.c165 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
169 ddc->regs = &ddc_data_regs[en]; in define_ddc_registers()
170 ddc->base.regs = &ddc_data_regs[en].gpio; in define_ddc_registers()
173 ddc->regs = &ddc_clk_regs[en]; in define_ddc_registers()
174 ddc->base.regs = &ddc_clk_regs[en].gpio; in define_ddc_registers()
181 ddc->shifts = &ddc_shift; in define_ddc_registers()
182 ddc->masks = &ddc_mask; in define_ddc_registers()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
Dhw_factory_dcn21.c173 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
177 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
178 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
181 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
182 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
189 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
190 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
Dhw_factory_dcn20.c183 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
187 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
188 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
191 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
192 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
199 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
200 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
Dhw_factory_dcn30.c200 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
204 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
205 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
208 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
209 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
216 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
217 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
Dhw_factory_dcn315.c194 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
198 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
199 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
202 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
203 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
210 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
211 ddc->masks = &ddc_mask[en]; in define_ddc_registers()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
Dhw_factory_dcn32.c204 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); in define_ddc_registers() local
208 ddc->regs = &ddc_data_regs_dcn[en]; in define_ddc_registers()
209 ddc->base.regs = &ddc_data_regs_dcn[en].gpio; in define_ddc_registers()
212 ddc->regs = &ddc_clk_regs_dcn[en]; in define_ddc_registers()
213 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; in define_ddc_registers()
220 ddc->shifts = &ddc_shift[en]; in define_ddc_registers()
221 ddc->masks = &ddc_mask[en]; in define_ddc_registers()

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