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/linux-6.1.9/arch/x86/lib/
Ddelay.c37 static void (*delay_halt_fn)(u64 start, u64 cycles) __ro_after_init;
63 static void delay_tsc(u64 cycles) in delay_tsc() argument
73 if ((now - bclock) >= cycles) in delay_tsc()
91 cycles -= (now - bclock); in delay_tsc()
105 static void delay_halt_tpause(u64 start, u64 cycles) in delay_halt_tpause() argument
107 u64 until = start + cycles; in delay_halt_tpause()
125 static void delay_halt_mwaitx(u64 unused, u64 cycles) in delay_halt_mwaitx() argument
129 delay = min_t(u64, MWAITX_MAX_WAIT_CYCLES, cycles); in delay_halt_mwaitx()
151 u64 start, end, cycles = __cycles; in delay_halt() local
157 if (!cycles) in delay_halt()
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/linux-6.1.9/tools/perf/dlfilters/
Ddlfilter-show-cycles.c19 static __u64 cycles[MAX_CPU][MAX_ENTRY]; variable
30 __u64 cycles[MAX_ENTRY]; member
77 e->cycles[pos] += cnt; in add_entry()
92 cycles[cpu][pos] += sample->cyc_cnt; in filter_event_early()
98 static void print_vals(__u64 cycles, __u64 delta) in print_vals() argument
101 printf("%10llu %10llu ", (unsigned long long)cycles, (unsigned long long)delta); in print_vals()
103 printf("%10llu %10s ", (unsigned long long)cycles, ""); in print_vals()
115 print_vals(cycles[cpu][pos], cycles[cpu][pos] - cycles_rpt[cpu][pos]); in filter_event()
116 cycles_rpt[cpu][pos] = cycles[cpu][pos]; in filter_event()
124 print_vals(e->cycles[pos], e->cycles[pos] - e->cycles_rpt[pos]); in filter_event()
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/linux-6.1.9/drivers/memory/
Djz4780-nemc.c163 uint32_t smcr, val, cycles; in jz4780_nemc_configure_bank() local
209 cycles = jz4780_nemc_ns_to_cycles(nemc, val); in jz4780_nemc_configure_bank()
210 if (cycles > nemc->soc_info->tas_tah_cycles_max) { in jz4780_nemc_configure_bank()
212 val, cycles); in jz4780_nemc_configure_bank()
216 smcr |= cycles << NEMC_SMCR_TAS_SHIFT; in jz4780_nemc_configure_bank()
221 cycles = jz4780_nemc_ns_to_cycles(nemc, val); in jz4780_nemc_configure_bank()
222 if (cycles > nemc->soc_info->tas_tah_cycles_max) { in jz4780_nemc_configure_bank()
224 val, cycles); in jz4780_nemc_configure_bank()
228 smcr |= cycles << NEMC_SMCR_TAH_SHIFT; in jz4780_nemc_configure_bank()
233 cycles = jz4780_nemc_ns_to_cycles(nemc, val); in jz4780_nemc_configure_bank()
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/linux-6.1.9/drivers/gpu/drm/i915/gt/
Dselftest_gt_pm.c43 u32 cycles[5]; in measure_clocks() local
48 cycles[i] = -ENGINE_READ_FW(engine, RING_TIMESTAMP); in measure_clocks()
54 cycles[i] += ENGINE_READ_FW(engine, RING_TIMESTAMP); in measure_clocks()
59 sort(cycles, 5, sizeof(*cycles), cmp_u32, NULL); in measure_clocks()
60 *out_cycles = (cycles[1] + 2 * cycles[2] + cycles[3]) / 4; in measure_clocks()
104 u32 cycles; in live_gt_clocks() local
112 measure_clocks(engine, &cycles, &dt); in live_gt_clocks()
114 time = intel_gt_clock_interval_to_ns(engine->gt, cycles); in live_gt_clocks()
118 engine->name, cycles, time, dt, expected, in live_gt_clocks()
128 if (9 * expected < 8 * cycles || 8 * expected > 9 * cycles) { in live_gt_clocks()
/linux-6.1.9/Documentation/devicetree/bindings/bus/
Dqcom,ebi2.txt34 FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
77 - qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
82 - qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
86 - qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
88 - qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
90 - qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
92 - qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
99 - qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
101 2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
102 - qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
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Dintel,ixp4xx-expansion-bus-controller.yaml62 description: Address timing, extend address phase with n cycles.
67 description: Setup chip select timing, extend setup phase with n cycles.
72 description: Strobe timing, extend strobe phase with n cycles.
77 description: Hold timing, extend hold phase with n cycles.
82 description: Recovery timing, extend recovery phase with n cycles.
87 description: The type of cycles to use on the expansion bus for this
88 chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
113 description: Enable write cycles.
/linux-6.1.9/tools/perf/Documentation/
Dintel-hybrid.txt45 For example, count the 'cycles' event on core cpus.
47 perf stat -e cpu_core/cycles/
56 For hardware events, they have pre-defined configs (e.g. 0 for cycles).
84 perf stat -e cycles -a (use system-wide in this example), two events
115 The kernel creates 'cycles' (0x400000000) on cpu0-cpu15 (core cpus),
116 and create 'cycles' (0x800000000) on cpu16-cpu23 (atom cpus).
122 6,744,979 cpu_core/cycles/
123 1,965,552 cpu_atom/cycles/
125 The first 'cycles' is core event, the second 'cycles' is atom event.
133 scaled value for core cycles is 160,444,092 and the percentage is 0.47%.
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Dperf-daemon.txt32 …916507 916508 ... \_ perf record --control=fifo:control,ack -m 10M -e cycles --overwrite --switc…
120 [session-cycles]
121 run = -m 10M -e cycles --overwrite --switch-output -a
136 [603350:cycles] perf record -m 10M -e cycles --overwrite --switch-output -a
149 [603350:cycles] perf record -m 10M -e cycles --overwrite --switch-output -a
150 base: /opt/perfdata/session-cycles
151 output: /opt/perfdata/session-cycles/output
152 control: /opt/perfdata/session-cycles/control
153 ack: /opt/perfdata/session-cycles/ack
173 OK cycles
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Dperf.data-directory-format.txt51 Samples for 'cycles' event do not have CPU attribute set. Skipping 'cpu' field.
55 … perf 15316 2060795.480902: 1 cycles: ffffffffa2caa548 native_write_msr+0x8 (vmlinux)
56 … perf 15316 2060795.480906: 1 cycles: ffffffffa2caa548 native_write_msr+0x8 (vmlinux)
57 … perf 15316 2060795.480908: 7 cycles: ffffffffa2caa548 native_write_msr+0x8 (vmlinux)
58 … perf 15316 2060795.480910: 119 cycles: ffffffffa2caa54a native_write_msr+0xa (vmlinux)
59 …perf 15316 2060795.480912: 2109 cycles: ffffffffa2c9b7b0 native_apic_msr_write+0x0 (vmlinux)
60 …perf 15316 2060795.480914: 37606 cycles: ffffffffa2f121fe perf_event_addr_filters_exec+0x2e …
61 …uname 15316 2060795.480924: 588287 cycles: ffffffffa303a56d page_counter_try_charge+0x6d (vml…
62 … uname 15316 2060795.481067: 2261945 cycles: ffffffffa301438f kmem_cache_free+0x4f (vmlinux)
63 …uname 15316 2060795.481643: 2172167 cycles: 7f1a48c393c0 _IO_un_link+0x0 (/lib/x86_64-linu…
/linux-6.1.9/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr3.yaml66 of clock cycles.
73 SELF REFRESH) in terms of number of clock cycles.
80 cycles.
86 Four-bank activate window in terms of number of clock cycles.
92 Mode register set command delay in terms of number of clock cycles.
99 of clock cycles.
105 Row active time in terms of number of clock cycles.
111 ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
117 RAS-to-CAS delay in terms of number of clock cycles.
123 Refresh Cycle time in terms of number of clock cycles.
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Djedec,lpddr2.yaml83 Active bank a to active bank b in terms of number of clock cycles.
90 Internal WRITE-to-READ command delay in terms of number of clock cycles.
98 cycles. Obtained from device datasheet.
105 cycles. Obtained from device datasheet.
112 of clock cycles. Obtained from device datasheet.
118 Row precharge time (all banks) in terms of number of clock cycles.
125 RAS-to-CAS delay in terms of number of clock cycles. Obtained from
132 WRITE recovery time in terms of number of clock cycles. Obtained from
139 Row active time in terms of number of clock cycles. Obtained from device
147 SELF REFRESH) in terms of number of clock cycles. Obtained from device
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/linux-6.1.9/Documentation/devicetree/bindings/mtd/
Dfsmc-nand.txt15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
17 cycles.
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
21 Only valid for write transactions. Zero means zero cycles,
22 255 means 255 cycles.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
25 one cycle, 255 means 256 cycles.
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
28 255 means 256 cycles.
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
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/linux-6.1.9/drivers/net/ethernet/mellanox/mlx4/
Den_clock.c44 container_of(tc, struct mlx4_en_dev, cycles); in mlx4_en_read_clock()
141 mdev->cycles.mult = neg_adj ? mult - diff : mult + diff; in mlx4_en_phc_adjfreq()
210 timecounter_init(&mdev->clock, &mdev->cycles, ns); in mlx4_en_phc_settime()
277 memset(&mdev->cycles, 0, sizeof(mdev->cycles)); in mlx4_en_init_timestamp()
278 mdev->cycles.read = mlx4_en_read_clock; in mlx4_en_init_timestamp()
279 mdev->cycles.mask = CLOCKSOURCE_MASK(48); in mlx4_en_init_timestamp()
280 mdev->cycles.shift = freq_to_shift(dev->caps.hca_core_clock); in mlx4_en_init_timestamp()
281 mdev->cycles.mult = in mlx4_en_init_timestamp()
282 clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift); in mlx4_en_init_timestamp()
283 mdev->nominal_c_mult = mdev->cycles.mult; in mlx4_en_init_timestamp()
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/linux-6.1.9/drivers/net/wireless/ath/
Dhw.c144 u32 cycles, busy, rx, tx; in ath_hw_cycle_counters_update() local
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
166 common->cc_ani.cycles += cycles; in ath_hw_cycle_counters_update()
171 common->cc_survey.cycles += cycles; in ath_hw_cycle_counters_update()
183 listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) / in ath_hw_get_listen_time()
/linux-6.1.9/arch/arm64/lib/
Ddelay.c26 void __delay(unsigned long cycles) in __delay() argument
31 u64 end = start + cycles; in __delay()
38 while ((get_cycles() - start) < cycles) in __delay()
44 while ((get_cycles() - start + timer_evt_period) < cycles) in __delay()
48 while ((get_cycles() - start) < cycles) in __delay()
/linux-6.1.9/drivers/pwm/
Dpwm-berlin.c96 u64 cycles; in berlin_pwm_config() local
98 cycles = clk_get_rate(bpc->clk); in berlin_pwm_config()
99 cycles *= period_ns; in berlin_pwm_config()
100 do_div(cycles, NSEC_PER_SEC); in berlin_pwm_config()
102 if (cycles > BERLIN_PWM_MAX_TCNT) { in berlin_pwm_config()
104 cycles >>= 12; // Prescaled by 4096 in berlin_pwm_config()
106 if (cycles > BERLIN_PWM_MAX_TCNT) in berlin_pwm_config()
110 period = cycles; in berlin_pwm_config()
111 cycles *= duty_ns; in berlin_pwm_config()
112 do_div(cycles, period_ns); in berlin_pwm_config()
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Dpwm-xilinx.c35 u64 cycles) in xilinx_timer_tlr_cycles() argument
37 WARN_ON(cycles < 2 || cycles - 2 > priv->max); in xilinx_timer_tlr_cycles()
40 return cycles - 2; in xilinx_timer_tlr_cycles()
41 return priv->max - cycles + 2; in xilinx_timer_tlr_cycles()
47 u64 cycles; in xilinx_timer_get_period() local
50 cycles = tlr + 2; in xilinx_timer_get_period()
52 cycles = (u64)priv->max - tlr + 2; in xilinx_timer_get_period()
55 return DIV64_U64_ROUND_UP(cycles * NSEC_PER_SEC, in xilinx_timer_get_period()
Dpwm-atmel.c199 unsigned long long cycles = state->period; in atmel_pwm_calculate_cprd_and_pres() local
203 cycles *= clkrate; in atmel_pwm_calculate_cprd_and_pres()
204 do_div(cycles, NSEC_PER_SEC); in atmel_pwm_calculate_cprd_and_pres()
211 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits; in atmel_pwm_calculate_cprd_and_pres()
218 cycles >>= *pres; in atmel_pwm_calculate_cprd_and_pres()
223 *cprd = cycles; in atmel_pwm_calculate_cprd_and_pres()
232 unsigned long long cycles = state->duty_cycle; in atmel_pwm_calculate_cdty() local
234 cycles *= clkrate; in atmel_pwm_calculate_cdty()
235 do_div(cycles, NSEC_PER_SEC); in atmel_pwm_calculate_cdty()
236 cycles >>= pres; in atmel_pwm_calculate_cdty()
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/linux-6.1.9/arch/xtensa/include/asm/
Ddelay.h40 unsigned long cycles = (usecs * (ccount_freq >> 15)) >> 5; in __udelay() local
43 while (((unsigned long)get_ccount()) - start < cycles) in __udelay()
61 unsigned long cycles = (nsec * (ccount_freq >> 15)) >> 15; in __ndelay() local
62 __delay(cycles); in __ndelay()
/linux-6.1.9/tools/virtio/ringtest/
Dmain.h20 static inline void wait_cycles(unsigned long long cycles) in wait_cycles() argument
25 while (__rdtsc() - t < cycles) {} in wait_cycles()
32 static inline void wait_cycles(unsigned long long cycles) in wait_cycles() argument
34 asm volatile("0: brctg %0,0b" : : "d" (cycles)); in wait_cycles()
42 static inline void wait_cycles(unsigned long long cycles) in wait_cycles() argument
/linux-6.1.9/tools/perf/tests/shell/
Dstat+shadow_stat.sh11 perf stat -a -e cycles sleep 1 2>&1 | grep -e cpu_core && exit 2
15 perf stat -a --no-big-num -e cycles,instructions sleep 1 2>&1 | \
16 grep -e cycles -e instructions | \
46 perf stat -a -A --no-big-num -e cycles,instructions sleep 1 2>&1 | \
/linux-6.1.9/tools/perf/util/
Dblock-info.c106 bi->cycles = ch->cycles; in init_block_info()
122 u64 cycles = 0; in block_info__process_sym() local
146 cycles += bi->cycles_aggr / bi->num_aggr; in block_info__process_sym()
158 *block_cycles_aggr += cycles; in block_info__process_sym()
229 static void cycles_string(u64 cycles, char *buf, int size) in cycles_string() argument
231 if (cycles >= 1000000) in cycles_string()
232 scnprintf(buf, size, "%.1fM", (double)cycles / 1000000.0); in cycles_string()
233 else if (cycles >= 1000) in cycles_string()
234 scnprintf(buf, size, "%.1fK", (double)cycles / 1000.0); in cycles_string()
236 scnprintf(buf, size, "%1d", cycles); in cycles_string()
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/linux-6.1.9/lib/vdso/
Dgettimeofday.c14 u64 vdso_calc_delta(u64 cycles, u64 last, u64 mask, u32 mult) in vdso_calc_delta() argument
16 return ((cycles - last) & mask) * mult; in vdso_calc_delta()
42 static inline bool vdso_cycles_ok(u64 cycles) in vdso_cycles_ok() argument
55 u64 cycles, last, ns; in do_hres_timens() local
73 cycles = __arch_get_hw_counter(vd->clock_mode, vd); in do_hres_timens()
74 if (unlikely(!vdso_cycles_ok(cycles))) in do_hres_timens()
78 ns += vdso_calc_delta(cycles, last, vd->mask, vd->mult); in do_hres_timens()
114 u64 cycles, last, sec, ns; in do_hres() local
144 cycles = __arch_get_hw_counter(vd->clock_mode, vd); in do_hres()
145 if (unlikely(!vdso_cycles_ok(cycles))) in do_hres()
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/linux-6.1.9/Documentation/m68k/
Dbuddha-driver.rst147 497ns Select (7 clock cycles) , IOR/IOW after 172ns (2 clock cycles)
152 639ns Select (9 clock cycles), IOR/IOW after 243ns (3 clock cycles)
155 781ns Select (11 clock cycles), IOR/IOW after 314ns (4 clock cycles)
158 355ns Select (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
161 355ns Select (5 clock cycles), IOR/IOW after 172ns (2 clock cycles)
164 355ns Select (5 clock cycles), IOR/IOW after 243ns (3 clock cycles)
167 1065ns Select (15 clock cycles), IOR/IOW after 314ns (4 clock cycles)
170 355ns Select, (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
176 781ns select, IOR/IOW after 4 clock cycles (=314ns) aktive.
180 system: Sometimes two more clock cycles are inserted by the
[all …]
/linux-6.1.9/arch/x86/include/asm/vdso/
Dgettimeofday.h288 static inline bool arch_vdso_cycles_ok(u64 cycles) in arch_vdso_cycles_ok() argument
290 return (s64)cycles >= 0; in arch_vdso_cycles_ok()
313 u64 vdso_calc_delta(u64 cycles, u64 last, u64 mask, u32 mult) in vdso_calc_delta() argument
315 if (cycles > last) in vdso_calc_delta()
316 return (cycles - last) * mult; in vdso_calc_delta()

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