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Searched refs:cw2 (Results 1 – 10 of 10) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_dcn30.c123 const struct dmub_window *cw2, in dmub_dcn30_setup_windows() argument
133 offset = cw2->offset; in dmub_dcn30_setup_windows()
135 if (cw2->region.base != cw2->region.top) { in dmub_dcn30_setup_windows()
138 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); in dmub_dcn30_setup_windows()
140 DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top, in dmub_dcn30_setup_windows()
Ddmub_dcn20.c190 const struct dmub_window *cw2, in dmub_dcn20_setup_windows() argument
201 if (cw2->region.base != cw2->region.top) { in dmub_dcn20_setup_windows()
202 dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, in dmub_dcn20_setup_windows()
207 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); in dmub_dcn20_setup_windows()
209 DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top, in dmub_dcn20_setup_windows()
Ddmub_dcn30.h42 const struct dmub_window *cw2,
Ddmub_srv.c516 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; in dmub_srv_hw_init() local
560 cw2.offset.quad_part = data_fb->gpu_addr; in dmub_srv_hw_init()
561 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; in dmub_srv_hw_init()
562 cw2.region.top = cw2.region.base + data_fb->size; in dmub_srv_hw_init()
600 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); in dmub_srv_hw_init()
Ddmub_dcn20.h196 const struct dmub_window *cw2,
Ddmub_dcn31.h198 const struct dmub_window *cw2,
Ddmub_dcn32.h200 const struct dmub_window *cw2,
Ddmub_dcn31.c186 const struct dmub_window *cw2, in dmub_dcn31_setup_windows() argument
Ddmub_dcn32.c209 const struct dmub_window *cw2, in dmub_dcn32_setup_windows() argument
/linux-6.1.9/drivers/gpu/drm/amd/display/dmub/
Ddmub_srv.h320 const struct dmub_window *cw2,