| /linux-6.1.9/drivers/edac/ |
| D | edac_mc.c | 128 mci->nr_csrows, mci->csrows); in edac_mc_dump_mci()
189 if (mci->csrows) { in mci_release()
191 csr = mci->csrows[row]; in mci_release()
202 kfree(mci->csrows); in mci_release()
218 mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); in edac_mc_alloc_csrows()
219 if (!mci->csrows) in edac_mc_alloc_csrows()
225 csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); in edac_mc_alloc_csrows()
229 mci->csrows[row] = csr; in edac_mc_alloc_csrows()
276 chan = mci->csrows[row]->channels[chn]; in edac_mc_alloc_dimms()
615 struct csrow_info *csrow = mci->csrows[i]; in edac_mc_add_mc_with_groups()
[all …]
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| D | pasemi_edac.c | 102 mci->csrows[cs]->first_page, 0, 0, in pasemi_edac_process_error_info()
109 mci->csrows[cs]->first_page, 0, 0, in pasemi_edac_process_error_info()
132 csrow = mci->csrows[index]; in pasemi_edac_init_csrows()
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| D | amd76x_edac.c | 148 mci->csrows[row]->first_page, 0, 0, in amd76x_process_error_info()
163 mci->csrows[row]->first_page, 0, 0, in amd76x_process_error_info()
195 csrow = mci->csrows[index]; in amd76x_init_csrows()
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| D | edac_mc_sysfs.c | 460 csrow = mci->csrows[i]; in edac_create_csrow_objects()
463 err = edac_create_csrow_object(mci, mci->csrows[i], i); in edac_create_csrow_objects()
471 if (device_is_registered(&mci->csrows[i]->dev)) in edac_create_csrow_objects()
472 device_unregister(&mci->csrows[i]->dev); in edac_create_csrow_objects()
483 if (device_is_registered(&mci->csrows[i]->dev)) in edac_delete_csrow_objects()
484 device_unregister(&mci->csrows[i]->dev); in edac_delete_csrow_objects()
697 struct csrow_info *ri = mci->csrows[row]; in mci_reset_counters_store()
827 struct csrow_info *csrow = mci->csrows[csrow_idx]; in mci_size_mb_show()
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| D | cell_edac.c | 37 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_count_ce()
60 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_count_ue()
130 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_init_csrows()
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| D | i82975x_edac.c | 310 chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1; in i82975x_process_error_info()
313 (1 << mci->csrows[row]->channels[chan]->dimm->grain)); in i82975x_process_error_info()
382 csrow = mci->csrows[index]; in i82975x_init_csrows()
407 dimm = mci->csrows[index]->channels[chan]->dimm; in i82975x_init_csrows()
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| D | aspeed_edac.c | 94 struct csrow_info *csrow = mci->csrows[0]; in count_rec()
127 struct csrow_info *csrow = mci->csrows[0]; in count_un_rec()
233 struct csrow_info *csrow = mci->csrows[0]; in init_csrows()
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| D | i82860_edac.c | 118 dimm = mci->csrows[row]->channels[0]->dimm; in i82860_process_error_info()
162 csrow = mci->csrows[index]; in i82860_init_csrows()
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| D | i3000_edac.c | 237 multi_chan = mci->csrows[0]->nr_channels - 1; in i3000_process_error_info()
392 struct csrow_info *csrow = mci->csrows[i]; in i3000_probe1()
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| D | i82875p_edac.c | 229 multi_chan = mci->csrows[0]->nr_channels - 1; in i82875p_process_error_info()
362 csrow = mci->csrows[index]; in i82875p_init_csrows()
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| D | cpc925_edac.c | 337 csrow = mci->csrows[index]; in cpc925_init_csrows()
452 if (mci->csrows[rank]->first_page == 0) { in cpc925_mc_get_pfn()
460 pa = mci->csrows[rank]->first_page << PAGE_SHIFT; in cpc925_mc_get_pfn()
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| D | fsl_ddr_edac.c | 319 csrow = mci->csrows[row_index]; in fsl_mc_check()
445 csrow = mci->csrows[index]; in fsl_ddr_init_csrows()
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| D | r82600_edac.c | 231 csrow = mci->csrows[index]; in r82600_init_csrows()
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| D | i82443bxgx_edac.c | 197 csrow = mci->csrows[index]; in i82443bxgx_init_csrows()
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| D | x38_edac.c | 373 struct csrow_info *csrow = mci->csrows[i]; in x38_probe1()
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| D | e7xxx_edac.c | 379 csrow = mci->csrows[index]; in e7xxx_init_csrows()
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| D | dmc520_edac.c | 460 csi = mci->csrows[row]; in dmc520_init_csrow()
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| D | ppc4xx_edac.c | 906 struct csrow_info *csi = mci->csrows[row]; in ppc4xx_edac_init_csrows()
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| D | e752x_edac.c | 1096 csrow = mci->csrows[remap_csrow_index(mci, index)]; in e752x_init_csrows()
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| D | synopsys_edac.c | 811 csi = mci->csrows[row]; in init_csrows()
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| D | amd64_edac.c | 3612 dimm = mci->csrows[cs]->channels[umc]->dimm; in init_csrows_df()
3666 csrow = mci->csrows[i]; in init_csrows()
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| /linux-6.1.9/Documentation/admin-guide/ |
| D | ras.rst | 329 There can be multiple csrows and multiple channels.
340 Memory controllers allow for several csrows, with 8 csrows being a
341 typical value. Yet, the actual number of csrows depends on the layout of
378 channel 1. Notice that there are two csrows possible on a physical DIMM.
379 These csrows are allocated their csrow assignment based on the slot into
381 Channel, the csrows cross both DIMMs.
1008 The minimum known unity is DIMMs. There are no information about csrows.
1009 As EDAC API maps the minimum unity is csrows, the driver sequentially
1010 maps channel/DIMM into different csrows.
1129 What happens here is that errors on different csrows, but at the same
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| /linux-6.1.9/include/linux/ |
| D | edac.h | 538 struct csrow_info **csrows; member
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