Home
last modified time | relevance | path

Searched refs:cptvf (Results 1 – 20 of 20) sorted by relevance

/linux-6.1.9/drivers/crypto/cavium/cpt/
Dcptvf_main.c16 void *cptvf; member
29 vq_post_process(cwqe->cptvf, cwqe->qno); in vq_work_handler()
32 static int init_worker_threads(struct cpt_vf *cptvf) in init_worker_threads() argument
34 struct pci_dev *pdev = cptvf->pdev; in init_worker_threads()
42 if (cptvf->nr_queues) { in init_worker_threads()
44 cptvf->nr_queues); in init_worker_threads()
47 for (i = 0; i < cptvf->nr_queues; i++) { in init_worker_threads()
51 cwqe_info->vq_wqe[i].cptvf = cptvf; in init_worker_threads()
54 cptvf->wqe_info = cwqe_info; in init_worker_threads()
59 static void cleanup_worker_threads(struct cpt_vf *cptvf) in cleanup_worker_threads() argument
[all …]
Dcptvf_mbox.c8 static void cptvf_send_msg_to_pf(struct cpt_vf *cptvf, struct cpt_mbox *mbx) in cptvf_send_msg_to_pf() argument
11 cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0), in cptvf_send_msg_to_pf()
13 cpt_write_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1), in cptvf_send_msg_to_pf()
18 void cptvf_handle_mbox_intr(struct cpt_vf *cptvf) in cptvf_handle_mbox_intr() argument
26 mbx.msg = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 0)); in cptvf_handle_mbox_intr()
27 mbx.data = cpt_read_csr64(cptvf->reg_base, CPTX_VFX_PF_MBOXX(0, 0, 1)); in cptvf_handle_mbox_intr()
28 dev_dbg(&cptvf->pdev->dev, "%s: Mailbox msg 0x%llx from PF\n", in cptvf_handle_mbox_intr()
33 cptvf->pf_acked = true; in cptvf_handle_mbox_intr()
34 cptvf->vfid = mbx.data; in cptvf_handle_mbox_intr()
35 dev_dbg(&cptvf->pdev->dev, "Received VFID %d\n", cptvf->vfid); in cptvf_handle_mbox_intr()
[all …]
Dcptvf_reqmanager.c44 static int setup_sgio_components(struct cpt_vf *cptvf, struct buf_ptr *list, in setup_sgio_components() argument
50 struct pci_dev *pdev = cptvf->pdev; in setup_sgio_components()
121 static inline int setup_sgio_list(struct cpt_vf *cptvf, in setup_sgio_list() argument
127 struct pci_dev *pdev = cptvf->pdev; in setup_sgio_list()
143 ret = setup_sgio_components(cptvf, req->in, in setup_sgio_list()
160 ret = setup_sgio_components(cptvf, req->out, in setup_sgio_list()
223 static int send_cpt_command(struct cpt_vf *cptvf, union cpt_inst_s *cmd, in send_cpt_command() argument
226 struct pci_dev *pdev = cptvf->pdev; in send_cpt_command()
233 if (unlikely(qno >= cptvf->nr_queues)) { in send_cpt_command()
235 qno, cptvf->nr_queues); in send_cpt_command()
[all …]
Dcptvf.h118 int cptvf_send_vf_up(struct cpt_vf *cptvf);
119 int cptvf_send_vf_down(struct cpt_vf *cptvf);
120 int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf);
121 int cptvf_send_vf_priority_msg(struct cpt_vf *cptvf);
122 int cptvf_send_vq_size_msg(struct cpt_vf *cptvf);
123 int cptvf_check_pf_ready(struct cpt_vf *cptvf);
124 void cptvf_handle_mbox_intr(struct cpt_vf *cptvf);
126 int cvm_crypto_init(struct cpt_vf *cptvf);
127 void vq_post_process(struct cpt_vf *cptvf, u32 qno);
128 void cptvf_write_vq_doorbell(struct cpt_vf *cptvf, u32 val);
DMakefile2 obj-$(CONFIG_CAVIUM_CPT) += cptpf.o cptvf.o
4 cptvf-objs := cptvf_main.o cptvf_reqmanager.o cptvf_mbox.o cptvf_algs.o
Drequest_manager.h91 struct cpt_vf *cptvf; member
144 void vq_post_process(struct cpt_vf *cptvf, u32 qno);
145 int process_request(struct cpt_vf *cptvf, struct cpt_request_info *req);
Dcptvf_algs.h116 int cptvf_do_request(void *cptvf, struct cpt_request_info *req);
Dcptvf_algs.c462 int cvm_crypto_init(struct cpt_vf *cptvf) in cvm_crypto_init() argument
464 struct pci_dev *pdev = cptvf->pdev; in cvm_crypto_init()
468 dev_handle.cdev[dev_count] = cptvf; in cvm_crypto_init()
/linux-6.1.9/drivers/crypto/marvell/octeontx/
Dotx_cptvf_main.c28 static int init_worker_threads(struct otx_cptvf *cptvf) in init_worker_threads() argument
30 struct pci_dev *pdev = cptvf->pdev; in init_worker_threads()
38 if (cptvf->num_queues) { in init_worker_threads()
40 cptvf->num_queues); in init_worker_threads()
43 for (i = 0; i < cptvf->num_queues; i++) { in init_worker_threads()
46 cwqe_info->vq_wqe[i].cptvf = cptvf; in init_worker_threads()
48 cptvf->wqe_info = cwqe_info; in init_worker_threads()
53 static void cleanup_worker_threads(struct otx_cptvf *cptvf) in cleanup_worker_threads() argument
55 struct pci_dev *pdev = cptvf->pdev; in cleanup_worker_threads()
59 cwqe_info = (struct otx_cptvf_wqe_info *)cptvf->wqe_info; in cleanup_worker_threads()
[all …]
Dotx_cptvf_mbox.c75 static void cptvf_send_msg_to_pf(struct otx_cptvf *cptvf, in cptvf_send_msg_to_pf() argument
79 writeq(mbx->msg, cptvf->reg_base + OTX_CPT_VFX_PF_MBOXX(0, 0)); in cptvf_send_msg_to_pf()
80 writeq(mbx->data, cptvf->reg_base + OTX_CPT_VFX_PF_MBOXX(0, 1)); in cptvf_send_msg_to_pf()
84 void otx_cptvf_handle_mbox_intr(struct otx_cptvf *cptvf) in otx_cptvf_handle_mbox_intr() argument
92 mbx.msg = readq(cptvf->reg_base + OTX_CPT_VFX_PF_MBOXX(0, 0)); in otx_cptvf_handle_mbox_intr()
93 mbx.data = readq(cptvf->reg_base + OTX_CPT_VFX_PF_MBOXX(0, 1)); in otx_cptvf_handle_mbox_intr()
99 cptvf->pf_acked = true; in otx_cptvf_handle_mbox_intr()
100 cptvf->num_vfs = mbx.data; in otx_cptvf_handle_mbox_intr()
103 cptvf->pf_acked = true; in otx_cptvf_handle_mbox_intr()
104 cptvf->vfid = mbx.data; in otx_cptvf_handle_mbox_intr()
[all …]
Dotx_cptvf.h62 struct otx_cptvf *cptvf; member
95 int otx_cptvf_send_vf_up(struct otx_cptvf *cptvf);
96 int otx_cptvf_send_vf_down(struct otx_cptvf *cptvf);
97 int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group);
98 int otx_cptvf_send_vf_priority_msg(struct otx_cptvf *cptvf);
99 int otx_cptvf_send_vq_size_msg(struct otx_cptvf *cptvf);
100 int otx_cptvf_check_pf_ready(struct otx_cptvf *cptvf);
101 void otx_cptvf_handle_mbox_intr(struct otx_cptvf *cptvf);
102 void otx_cptvf_write_vq_doorbell(struct otx_cptvf *cptvf, u32 val);
Dotx_cptvf_reqmgr.c268 static void cpt_send_cmd(union otx_cpt_inst_s *cptinst, struct otx_cptvf *cptvf) in cpt_send_cmd() argument
270 struct otx_cpt_cmd_qinfo *qinfo = &cptvf->cqinfo; in cpt_send_cmd()
294 otx_cptvf_write_vq_doorbell(cptvf, 1); in cpt_send_cmd()
299 struct otx_cptvf *cptvf) in process_request() argument
386 cpt_send_cmd(&cptinst, cptvf); in process_request()
407 struct otx_cptvf *cptvf = pci_get_drvdata(pdev); in otx_cpt_do_request() local
409 if (!otx_cpt_device_ready(cptvf)) { in otx_cpt_do_request()
414 if ((cptvf->vftype == OTX_CPT_SE_TYPES) && (!req->ctrl.s.se_req)) { in otx_cpt_do_request()
416 cptvf->vfid); in otx_cpt_do_request()
418 } else if ((cptvf->vftype == OTX_CPT_AE_TYPES) && in otx_cpt_do_request()
[all …]
DMakefile2 obj-$(CONFIG_CRYPTO_DEV_OCTEONTX_CPT) += octeontx-cpt.o octeontx-cptvf.o
5 octeontx-cptvf-objs := otx_cptvf_main.o otx_cptvf_mbox.o otx_cptvf_reqmgr.o \
/linux-6.1.9/drivers/crypto/marvell/octeontx2/
Dotx2_cptvf_main.c13 static void cptvf_enable_pfvf_mbox_intrs(struct otx2_cptvf_dev *cptvf) in cptvf_enable_pfvf_mbox_intrs() argument
16 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT, in cptvf_enable_pfvf_mbox_intrs()
20 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, in cptvf_enable_pfvf_mbox_intrs()
24 static void cptvf_disable_pfvf_mbox_intrs(struct otx2_cptvf_dev *cptvf) in cptvf_disable_pfvf_mbox_intrs() argument
27 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, in cptvf_disable_pfvf_mbox_intrs()
31 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT, in cptvf_disable_pfvf_mbox_intrs()
35 static int cptvf_register_interrupts(struct otx2_cptvf_dev *cptvf) in cptvf_register_interrupts() argument
40 num_vec = pci_msix_vec_count(cptvf->pdev); in cptvf_register_interrupts()
45 ret = pci_alloc_irq_vectors(cptvf->pdev, num_vec, num_vec, in cptvf_register_interrupts()
48 dev_err(&cptvf->pdev->dev, in cptvf_register_interrupts()
[all …]
Dotx2_cptvf_mbox.c8 int otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev *cptvf, struct pci_dev *pdev) in otx2_cpt_mbox_bbuf_init() argument
13 cptvf->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); in otx2_cpt_mbox_bbuf_init()
14 if (!cptvf->bbuf_base) in otx2_cpt_mbox_bbuf_init()
21 otx2_mbox = &cptvf->pfvf_mbox; in otx2_cpt_mbox_bbuf_init()
23 mdev->mbase = cptvf->bbuf_base; in otx2_cpt_mbox_bbuf_init()
52 struct otx2_cptvf_dev *cptvf = arg; in otx2_cptvf_pfvf_mbox_intr() local
56 intr = otx2_cpt_read64(cptvf->reg_base, BLKADDR_RVUM, 0, in otx2_cptvf_pfvf_mbox_intr()
61 queue_work(cptvf->pfvf_mbox_wq, &cptvf->pfvf_mbox_work); in otx2_cptvf_pfvf_mbox_intr()
63 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, in otx2_cptvf_pfvf_mbox_intr()
69 static void process_pfvf_mbox_mbox_msg(struct otx2_cptvf_dev *cptvf, in process_pfvf_mbox_mbox_msg() argument
[all …]
Dcn10k_cpt.c72 int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf) in cn10k_cptvf_lmtst_init() argument
74 struct pci_dev *pdev = cptvf->pdev; in cn10k_cptvf_lmtst_init()
77 if (!test_bit(CN10K_LMTST, &cptvf->cap_flag)) { in cn10k_cptvf_lmtst_init()
78 cptvf->lfs.ops = &otx2_hw_ops; in cn10k_cptvf_lmtst_init()
82 cptvf->lfs.ops = &cn10k_hw_ops; in cn10k_cptvf_lmtst_init()
86 cptvf->lfs.lmt_base = devm_ioremap_wc(&pdev->dev, offset, size); in cn10k_cptvf_lmtst_init()
87 if (!cptvf->lfs.lmt_base) { in cn10k_cptvf_lmtst_init()
Dotx2_cptvf.h28 int otx2_cptvf_send_eng_grp_num_msg(struct otx2_cptvf_dev *cptvf, int eng_type);
29 int otx2_cptvf_send_kvf_limits_msg(struct otx2_cptvf_dev *cptvf);
30 int otx2_cpt_mbox_bbuf_init(struct otx2_cptvf_dev *cptvf, struct pci_dev *pdev);
Dcn10k_cpt.h34 int cn10k_cptvf_lmtst_init(struct otx2_cptvf_dev *cptvf);
Dotx2_cptvf_reqmgr.c345 struct otx2_cptvf_dev *cptvf = pci_get_drvdata(pdev); in otx2_cpt_do_request() local
346 struct otx2_cptlfs_info *lfs = &cptvf->lfs; in otx2_cpt_do_request()
541 struct otx2_cptvf_dev *cptvf = pci_get_drvdata(pdev); in otx2_cpt_get_kcrypto_eng_grp_num() local
543 return cptvf->lfs.kcrypto_eng_grp_num; in otx2_cpt_get_kcrypto_eng_grp_num()
/linux-6.1.9/drivers/crypto/marvell/
DKconfig37 the modules will be called octeontx-cpt and octeontx-cptvf