Searched refs:cp_hqd_pq_wptr_poll_addr_hi (Results 1 – 21 of 21) sorted by relevance
93 uint32_t cp_hqd_pq_wptr_poll_addr_hi; member
302 uint32_t cp_hqd_pq_wptr_poll_addr_hi; member
817 uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E) member
819 uint32_t cp_hqd_pq_wptr_poll_addr_hi; member
203 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
177 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
226 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
191 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in __update_mqd()
766 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v10_1_mqd_init()864 mqd->cp_hqd_pq_wptr_poll_addr_hi);
329 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in kgd_hiq_mqd_load()
301 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in hiq_mqd_load_v11()
817 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v11_0_mqd_init()911 mqd->cp_hqd_pq_wptr_poll_addr_hi); in mes_v11_0_queue_init_register()
341 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in kgd_gfx_v9_hiq_mqd_load()
316 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); in hiq_mqd_load_v10_3()
2810 u32 cp_hqd_pq_wptr_poll_addr_hi; member2950 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v7_0_mqd_init()
3845 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v11_0_compute_mqd_init()3963 mqd->cp_hqd_pq_wptr_poll_addr_hi); in gfx_v11_0_kiq_init_register()
3369 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v9_0_mqd_init()3470 mqd->cp_hqd_pq_wptr_poll_addr_hi); in gfx_v9_0_kiq_init_register()
6755 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v10_0_compute_mqd_init()6855 mqd->cp_hqd_pq_wptr_poll_addr_hi); in gfx_v10_0_kiq_init_register()
4512 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in gfx_v8_0_mqd_init()
4448 u32 cp_hqd_pq_wptr_poll_addr_hi; member4681 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in cik_cp_compute_resume()4684 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi); in cik_cp_compute_resume()