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Searched refs:cmdq (Results 1 – 25 of 53) sorted by relevance

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/linux-6.1.9/drivers/infiniband/hw/erdma/
Derdma_cmdq.c9 static void arm_cmdq_cq(struct erdma_cmdq *cmdq) in arm_cmdq_cq() argument
11 struct erdma_dev *dev = container_of(cmdq, struct erdma_dev, cmdq); in arm_cmdq_cq()
12 u64 db_data = FIELD_PREP(ERDMA_CQDB_CI_MASK, cmdq->cq.ci) | in arm_cmdq_cq()
14 FIELD_PREP(ERDMA_CQDB_CMDSN_MASK, cmdq->cq.cmdsn) | in arm_cmdq_cq()
15 FIELD_PREP(ERDMA_CQDB_IDX_MASK, cmdq->cq.cmdsn); in arm_cmdq_cq()
17 *cmdq->cq.db_record = db_data; in arm_cmdq_cq()
20 atomic64_inc(&cmdq->cq.armed_num); in arm_cmdq_cq()
23 static void kick_cmdq_db(struct erdma_cmdq *cmdq) in kick_cmdq_db() argument
25 struct erdma_dev *dev = container_of(cmdq, struct erdma_dev, cmdq); in kick_cmdq_db()
26 u64 db_data = FIELD_PREP(ERDMA_CMD_HDR_WQEBB_INDEX_MASK, cmdq->sq.pi); in kick_cmdq_db()
[all …]
Derdma.h204 struct erdma_cmdq cmdq; member
274 int erdma_post_cmd_wait(struct erdma_cmdq *cmdq, void *req, u32 req_size,
276 void erdma_cmdq_completion_handler(struct erdma_cmdq *cmdq);
/linux-6.1.9/drivers/gpu/drm/nouveau/nvkm/falcon/
Dcmdq.c26 nvkm_falcon_cmdq_has_room(struct nvkm_falcon_cmdq *cmdq, u32 size, bool *rewind) in nvkm_falcon_cmdq_has_room() argument
28 u32 head = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->head_reg); in nvkm_falcon_cmdq_has_room()
29 u32 tail = nvkm_falcon_rd32(cmdq->qmgr->falcon, cmdq->tail_reg); in nvkm_falcon_cmdq_has_room()
35 free = cmdq->offset + cmdq->size - head; in nvkm_falcon_cmdq_has_room()
40 head = cmdq->offset; in nvkm_falcon_cmdq_has_room()
51 nvkm_falcon_cmdq_push(struct nvkm_falcon_cmdq *cmdq, void *data, u32 size) in nvkm_falcon_cmdq_push() argument
53 struct nvkm_falcon *falcon = cmdq->qmgr->falcon; in nvkm_falcon_cmdq_push()
54 nvkm_falcon_load_dmem(falcon, data, cmdq->position, size, 0); in nvkm_falcon_cmdq_push()
55 cmdq->position += ALIGN(size, QUEUE_ALIGNMENT); in nvkm_falcon_cmdq_push()
59 nvkm_falcon_cmdq_rewind(struct nvkm_falcon_cmdq *cmdq) in nvkm_falcon_cmdq_rewind() argument
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DKbuild3 nvkm-y += nvkm/falcon/cmdq.o
/linux-6.1.9/drivers/mailbox/
Dmtk-cmdq-mailbox.c65 struct cmdq *cmdq; member
72 struct cmdq { struct
95 struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox); in cmdq_get_shift_pa() local
97 return cmdq->shift_pa; in cmdq_get_shift_pa()
101 static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread) in cmdq_thread_suspend() argument
113 dev_err(cmdq->mbox.dev, "suspend GCE thread 0x%x failed\n", in cmdq_thread_suspend()
114 (u32)(thread->base - cmdq->base)); in cmdq_thread_suspend()
126 static void cmdq_init(struct cmdq *cmdq) in cmdq_init() argument
130 WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); in cmdq_init()
131 if (cmdq->control_by_sw) in cmdq_init()
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DMakefile54 obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o
/linux-6.1.9/drivers/crypto/cavium/nitrox/
Dnitrox_lib.c25 static int nitrox_cmdq_init(struct nitrox_cmdq *cmdq, int align_bytes) in nitrox_cmdq_init() argument
27 struct nitrox_device *ndev = cmdq->ndev; in nitrox_cmdq_init()
29 cmdq->qsize = (ndev->qlen * cmdq->instr_size) + align_bytes; in nitrox_cmdq_init()
30 cmdq->unalign_base = dma_alloc_coherent(DEV(ndev), cmdq->qsize, in nitrox_cmdq_init()
31 &cmdq->unalign_dma, in nitrox_cmdq_init()
33 if (!cmdq->unalign_base) in nitrox_cmdq_init()
36 cmdq->dma = PTR_ALIGN(cmdq->unalign_dma, align_bytes); in nitrox_cmdq_init()
37 cmdq->base = cmdq->unalign_base + (cmdq->dma - cmdq->unalign_dma); in nitrox_cmdq_init()
38 cmdq->write_idx = 0; in nitrox_cmdq_init()
40 spin_lock_init(&cmdq->cmd_qlock); in nitrox_cmdq_init()
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Dnitrox_reqmgr.c230 struct nitrox_cmdq *cmdq) in backlog_list_add() argument
234 spin_lock_bh(&cmdq->backlog_qlock); in backlog_list_add()
235 list_add_tail(&sr->backlog, &cmdq->backlog_head); in backlog_list_add()
236 atomic_inc(&cmdq->backlog_count); in backlog_list_add()
238 spin_unlock_bh(&cmdq->backlog_qlock); in backlog_list_add()
242 struct nitrox_cmdq *cmdq) in response_list_add() argument
246 spin_lock_bh(&cmdq->resp_qlock); in response_list_add()
247 list_add_tail(&sr->response, &cmdq->response_head); in response_list_add()
248 spin_unlock_bh(&cmdq->resp_qlock); in response_list_add()
252 struct nitrox_cmdq *cmdq) in response_list_del() argument
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Dnitrox_isr.c32 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr() local
34 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
337 qvec->cmdq = &ndev->pkt_inq[qvec->ring]; in nitrox_register_interrupts()
Dnitrox_hal.c125 struct nitrox_cmdq *cmdq = &ndev->pkt_inq[i]; in nitrox_config_pkt_input_rings() local
138 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_pkt_input_rings()
357 struct nitrox_cmdq *cmdq = ndev->aqmq[ring]; in nitrox_config_aqm_rings() local
380 nitrox_write_csr(ndev, offset, cmdq->dma); in nitrox_config_aqm_rings()
/linux-6.1.9/drivers/net/ethernet/brocade/bna/
Dbfa_msgq.c31 static void bfa_msgq_cmdq_dbell(struct bfa_msgq_cmdq *cmdq);
32 static void bfa_msgq_cmdq_copy_rsp(struct bfa_msgq_cmdq *cmdq);
43 bfa_fsm_state_decl(cmdq, stopped, struct bfa_msgq_cmdq, enum cmdq_event);
44 bfa_fsm_state_decl(cmdq, init_wait, struct bfa_msgq_cmdq, enum cmdq_event);
45 bfa_fsm_state_decl(cmdq, ready, struct bfa_msgq_cmdq, enum cmdq_event);
46 bfa_fsm_state_decl(cmdq, dbell_wait, struct bfa_msgq_cmdq,
50 cmdq_sm_stopped_entry(struct bfa_msgq_cmdq *cmdq) in cmdq_sm_stopped_entry() argument
54 cmdq->producer_index = 0; in cmdq_sm_stopped_entry()
55 cmdq->consumer_index = 0; in cmdq_sm_stopped_entry()
56 cmdq->flags = 0; in cmdq_sm_stopped_entry()
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/linux-6.1.9/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_cmdq.c78 #define cmdq_to_cmdqs(cmdq) container_of((cmdq) - (cmdq)->cmdq_type, \ argument
79 struct hinic_cmdqs, cmdq[0])
320 static void cmdq_set_db(struct hinic_cmdq *cmdq, in cmdq_set_db() argument
332 writel(db_info, CMDQ_DB_ADDR(cmdq->db_base, prod_idx)); in cmdq_set_db()
335 static int cmdq_sync_cmd_direct_resp(struct hinic_cmdq *cmdq, in cmdq_sync_cmd_direct_resp() argument
343 struct hinic_wq *wq = cmdq->wq; in cmdq_sync_cmd_direct_resp()
348 spin_lock_bh(&cmdq->cmdq_lock); in cmdq_sync_cmd_direct_resp()
353 spin_unlock_bh(&cmdq->cmdq_lock); in cmdq_sync_cmd_direct_resp()
359 wrapped = cmdq->wrapped; in cmdq_sync_cmd_direct_resp()
364 cmdq->wrapped = !cmdq->wrapped; in cmdq_sync_cmd_direct_resp()
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Dhinic_hw_io.c533 enum hinic_cmdq_type cmdq, type; in hinic_io_init() local
565 for (cmdq = HINIC_CMDQ_SYNC; cmdq < HINIC_MAX_CMDQ_TYPES; cmdq++) { in hinic_io_init()
573 func_to_io->cmdq_db_area[cmdq] = db_area; in hinic_io_init()
600 for (type = HINIC_CMDQ_SYNC; type < cmdq; type++) in hinic_io_init()
619 enum hinic_cmdq_type cmdq; in hinic_io_free() local
628 for (cmdq = HINIC_CMDQ_SYNC; cmdq < HINIC_MAX_CMDQ_TYPES; cmdq++) in hinic_io_free()
629 return_db_area(func_to_io, func_to_io->cmdq_db_area[cmdq]); in hinic_io_free()
/linux-6.1.9/drivers/infiniband/hw/bnxt_re/
Dqplib_rcfw.c58 struct bnxt_qplib_cmdq_ctx *cmdq; in __wait_for_resp() local
62 cmdq = &rcfw->cmdq; in __wait_for_resp()
64 rc = wait_event_timeout(cmdq->waitq, in __wait_for_resp()
65 !test_bit(cbit, cmdq->cmdq_bitmap), in __wait_for_resp()
73 struct bnxt_qplib_cmdq_ctx *cmdq; in __block_for_resp() local
76 cmdq = &rcfw->cmdq; in __block_for_resp()
78 if (!test_bit(cbit, cmdq->cmdq_bitmap)) in __block_for_resp()
83 } while (test_bit(cbit, cmdq->cmdq_bitmap) && --count); in __block_for_resp()
91 struct bnxt_qplib_cmdq_ctx *cmdq = &rcfw->cmdq; in __send_message() local
92 struct bnxt_qplib_hwq *hwq = &cmdq->hwq; in __send_message()
[all …]
/linux-6.1.9/drivers/net/ethernet/hisilicon/hns3/hns3_common/
Dhclge_comm_cmd.c495 struct hclge_comm_cmq *cmdq = &hw->cmq; in hclge_comm_cmd_uninit() local
504 spin_lock_bh(&cmdq->csq.lock); in hclge_comm_cmd_uninit()
505 spin_lock(&cmdq->crq.lock); in hclge_comm_cmd_uninit()
507 spin_unlock(&cmdq->crq.lock); in hclge_comm_cmd_uninit()
508 spin_unlock_bh(&cmdq->csq.lock); in hclge_comm_cmd_uninit()
510 hclge_comm_free_cmd_desc(&cmdq->csq); in hclge_comm_cmd_uninit()
511 hclge_comm_free_cmd_desc(&cmdq->crq); in hclge_comm_cmd_uninit()
516 struct hclge_comm_cmq *cmdq = &hw->cmq; in hclge_comm_cmd_queue_init() local
520 spin_lock_init(&cmdq->csq.lock); in hclge_comm_cmd_queue_init()
521 spin_lock_init(&cmdq->crq.lock); in hclge_comm_cmd_queue_init()
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/linux-6.1.9/drivers/iommu/arm/arm-smmu-v3/
Darm-smmu-v3.c338 return &smmu->cmdq; in arm_smmu_get_cmdq()
417 __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); in arm_smmu_cmdq_skip_err()
432 static void arm_smmu_cmdq_shared_lock(struct arm_smmu_cmdq *cmdq) in arm_smmu_cmdq_shared_lock() argument
442 if (atomic_fetch_inc_relaxed(&cmdq->lock) >= 0) in arm_smmu_cmdq_shared_lock()
446 val = atomic_cond_read_relaxed(&cmdq->lock, VAL >= 0); in arm_smmu_cmdq_shared_lock()
447 } while (atomic_cmpxchg_relaxed(&cmdq->lock, val, val + 1) != val); in arm_smmu_cmdq_shared_lock()
450 static void arm_smmu_cmdq_shared_unlock(struct arm_smmu_cmdq *cmdq) in arm_smmu_cmdq_shared_unlock() argument
452 (void)atomic_dec_return_release(&cmdq->lock); in arm_smmu_cmdq_shared_unlock()
455 static bool arm_smmu_cmdq_shared_tryunlock(struct arm_smmu_cmdq *cmdq) in arm_smmu_cmdq_shared_tryunlock() argument
457 if (atomic_read(&cmdq->lock) == 1) in arm_smmu_cmdq_shared_tryunlock()
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/linux-6.1.9/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
Dbase.c61 nvkm_falcon_cmdq_fini(sec2->cmdq); in nvkm_sec2_fini()
73 nvkm_falcon_cmdq_del(&sec2->cmdq); in nvkm_sec2_dtor()
112 (ret = nvkm_falcon_cmdq_new(sec2->qmgr, "cmdq", &sec2->cmdq)) || in nvkm_sec2_new_()
Dgp102.c71 return nvkm_falcon_cmdq_send(sec2->cmdq, &cmd.cmd.hdr, in gp102_sec2_acr_bootstrap_falcon()
153 nvkm_falcon_cmdq_init(sec2->cmdq, in gp102_sec2_initmsg()
246 .cmdq = { 0xa00, 0xa04, 8 },
Dtu102.c40 .cmdq = { 0xc00, 0xc04, 8 },
/linux-6.1.9/drivers/atm/
Dfore200e.c556 struct host_cmdq* cmdq = &fore200e->host_cmdq; in fore200e_pca_prom_read() local
557 struct host_cmdq_entry* entry = &cmdq->host_entry[ cmdq->head ]; in fore200e_pca_prom_read()
562 FORE200E_NEXT_ENTRY(cmdq->head, QUEUE_SIZE_CMD); in fore200e_pca_prom_read()
1225 struct host_cmdq* cmdq = &fore200e->host_cmdq; in fore200e_activate_vcin() local
1226 struct host_cmdq_entry* entry = &cmdq->host_entry[ cmdq->head ]; in fore200e_activate_vcin()
1233 FORE200E_NEXT_ENTRY(cmdq->head, QUEUE_SIZE_CMD); in fore200e_activate_vcin()
1669 struct host_cmdq* cmdq = &fore200e->host_cmdq; in fore200e_getstats() local
1670 struct host_cmdq_entry* entry = &cmdq->host_entry[ cmdq->head ]; in fore200e_getstats()
1686 FORE200E_NEXT_ENTRY(cmdq->head, QUEUE_SIZE_CMD); in fore200e_getstats()
1715 struct host_cmdq* cmdq = &fore200e->host_cmdq;
[all …]
/linux-6.1.9/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml45 - cmdq-sync # CMD_SYNC complete
91 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
/linux-6.1.9/drivers/media/platform/mediatek/mdp3/
DMakefile4 mtk-mdp3-y += mtk-mdp3-comp.o mtk-mdp3-cmdq.o
/linux-6.1.9/drivers/gpu/drm/nouveau/include/nvkm/engine/
Dsec2.h14 struct nvkm_falcon_cmdq *cmdq; member
/linux-6.1.9/drivers/soc/mediatek/
DMakefile2 obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
/linux-6.1.9/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgm200.c51 .cmdq = { 0x4a0, 0x4b0, 4 },

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