| /linux-6.1.9/drivers/clk/samsung/ |
| D | clk-s5pv210-audss.c | 69 struct clk_hw **clk_table; in s5pv210_audss_clk_probe() local
84 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
113 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", in s5pv210_audss_clk_probe()
124 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", in s5pv210_audss_clk_probe()
129 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
132 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
136 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", in s5pv210_audss_clk_probe()
142 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", in s5pv210_audss_clk_probe()
145 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", in s5pv210_audss_clk_probe()
148 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", in s5pv210_audss_clk_probe()
[all …]
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| D | clk-s3c2410-dclk.c | 245 struct clk_hw **clk_table; in s3c24xx_dclk_probe() local
255 clk_table = s3c24xx_dclk->clk_data.hws; in s3c24xx_dclk_probe()
270 clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0", in s3c24xx_dclk_probe()
275 clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1", in s3c24xx_dclk_probe()
281 clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0", in s3c24xx_dclk_probe()
284 clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1", in s3c24xx_dclk_probe()
288 clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0", in s3c24xx_dclk_probe()
292 clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1", in s3c24xx_dclk_probe()
297 clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev, in s3c24xx_dclk_probe()
300 clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev, in s3c24xx_dclk_probe()
[all …]
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| D | clk-exynos-audss.c | 131 struct clk_hw **clk_table; in exynos_audss_clk_probe() local
153 clk_table = clk_data->hws; in exynos_audss_clk_probe()
184 clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss", in exynos_audss_clk_probe()
195 clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s", in exynos_audss_clk_probe()
200 clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp", in exynos_audss_clk_probe()
204 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev, in exynos_audss_clk_probe()
208 clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s", in exynos_audss_clk_probe()
212 clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk", in exynos_audss_clk_probe()
216 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus", in exynos_audss_clk_probe()
220 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s", in exynos_audss_clk_probe()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 558 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn31_update_bw_bounding_box() local
574 ASSERT(clk_table->num_entries); in dcn31_update_bw_bounding_box()
577 for (i = 0; i < clk_table->num_entries; ++i) { in dcn31_update_bw_bounding_box()
578 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn31_update_bw_bounding_box()
579 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn31_update_bw_bounding_box()
580 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn31_update_bw_bounding_box()
581 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn31_update_bw_bounding_box()
584 for (i = 0; i < clk_table->num_entries; i++) { in dcn31_update_bw_bounding_box()
587 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
596 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| D | dcn321_fpu.c | 274 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in build_synthetic_soc_states()
275 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_synthetic_soc_states()
276 if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz) in build_synthetic_soc_states()
277 max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; in build_synthetic_soc_states()
278 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) in build_synthetic_soc_states()
279 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; in build_synthetic_soc_states()
280 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in build_synthetic_soc_states()
281 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in build_synthetic_soc_states()
282 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in build_synthetic_soc_states()
283 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in build_synthetic_soc_states()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| D | dcn315_clk_mgr.c | 237 .clk_table = {
386 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn315_build_watermark_ranges()
389 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn315_build_watermark_ranges()
482 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn315_clk_mgr_helper_populate_bw_params()
506 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) in dcn315_clk_mgr_helper_populate_bw_params()
507 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn315_clk_mgr_helper_populate_bw_params()
509 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
510 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
511 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
514 bw_params->clk_table.entries[i].fclk_mhz = min_fclk; in dcn315_clk_mgr_helper_populate_bw_params()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.c | 354 .clk_table = {
461 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn314_build_watermark_ranges()
464 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn314_build_watermark_ranges()
574 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn314_clk_mgr_helper_populate_bw_params()
615 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) in dcn314_clk_mgr_helper_populate_bw_params()
616 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn314_clk_mgr_helper_populate_bw_params()
619 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
620 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
621 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
624 bw_params->clk_table.entries[i].fclk_mhz = min_fclk; in dcn314_clk_mgr_helper_populate_bw_params()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| D | dcn302_fpu.c | 220 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn302_fpu_update_bw_bounding_box()
224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box()
225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
226 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn302_fpu_update_bw_bounding_box()
227 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn302_fpu_update_bw_bounding_box()
228 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn302_fpu_update_bw_bounding_box()
229 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
230 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn302_fpu_update_bw_bounding_box()
231 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn302_fpu_update_bw_bounding_box()
258 num_uclk_states = bw_params->clk_table.num_entries; in dcn302_fpu_update_bw_bounding_box()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | dcn314_fpu.c | 182 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn314_update_bw_bounding_box_fpu() local
204 ASSERT(clk_table->num_entries); in dcn314_update_bw_bounding_box_fpu()
207 for (i = 0; i < clk_table->num_entries; ++i) { in dcn314_update_bw_bounding_box_fpu()
208 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn314_update_bw_bounding_box_fpu()
209 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn314_update_bw_bounding_box_fpu()
210 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn314_update_bw_bounding_box_fpu()
211 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn314_update_bw_bounding_box_fpu()
214 for (i = 0; i < clk_table->num_entries; i++) { in dcn314_update_bw_bounding_box_fpu()
217 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu()
222 if (clk_table->num_entries == 1) { in dcn314_update_bw_bounding_box_fpu()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| D | dcn303_fpu.c | 216 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn303_fpu_update_bw_bounding_box()
220 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn303_fpu_update_bw_bounding_box()
221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
222 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn303_fpu_update_bw_bounding_box()
223 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn303_fpu_update_bw_bounding_box()
224 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn303_fpu_update_bw_bounding_box()
225 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
226 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn303_fpu_update_bw_bounding_box()
227 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn303_fpu_update_bw_bounding_box()
252 num_uclk_states = bw_params->clk_table.num_entries; in dcn303_fpu_update_bw_bounding_box()
[all …]
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| /linux-6.1.9/drivers/clk/mmp/ |
| D | clk.c | 13 struct clk **clk_table; in mmp_clk_init() local
15 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in mmp_clk_init()
16 if (!clk_table) in mmp_clk_init()
19 unit->clk_table = clk_table; in mmp_clk_init()
21 unit->clk_data.clks = clk_table; in mmp_clk_init()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
66 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
92 unit->clk_table[clks[i].id] = clk; in mmp_register_general_gate_clks()
120 unit->clk_table[clks[i].id] = clk; in mmp_register_gate_clks()
148 unit->clk_table[clks[i].id] = clk; in mmp_register_mux_clks()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega10_processpptables.c | 572 phm_ppt_v1_clock_voltage_dependency_table *clk_table; in get_socclk_voltage_dependency_table() local
577 clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries), in get_socclk_voltage_dependency_table()
579 if (!clk_table) in get_socclk_voltage_dependency_table()
582 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries; in get_socclk_voltage_dependency_table()
585 clk_table->entries[i].vddInd = in get_socclk_voltage_dependency_table()
587 clk_table->entries[i].clk = in get_socclk_voltage_dependency_table()
591 *pp_vega10_clk_dep_table = clk_table; in get_socclk_voltage_dependency_table()
638 *clk_table; in get_gfxclk_voltage_dependency_table() local
644 clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries), in get_gfxclk_voltage_dependency_table()
646 if (!clk_table) in get_gfxclk_voltage_dependency_table()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| D | smu_v13_0_4_ppt.c | 410 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_4_get_dpm_freq_by_index() local
412 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_4_get_dpm_freq_by_index()
417 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
419 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
422 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
424 *freq = clk_table->VClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
427 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
429 *freq = clk_table->DClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
433 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
435 *freq = clk_table->DfPstateTable[dpm_level].MemClk; in smu_v13_0_4_get_dpm_freq_by_index()
[all …]
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| D | smu_v13_0_5_ppt.c | 620 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_5_get_dpm_level_count() local
624 *count = clk_table->NumSocClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
627 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
630 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
633 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
636 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
650 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_5_get_dpm_freq_by_index() local
652 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_5_get_dpm_freq_by_index()
657 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
659 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
[all …]
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| D | yellow_carp_ppt.c | 746 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in yellow_carp_get_dpm_level_count() local
750 *count = clk_table->NumSocClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
753 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
756 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
759 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
762 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
776 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in yellow_carp_get_dpm_freq_by_index() local
778 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
783 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in yellow_carp_get_dpm_freq_by_index()
785 *freq = clk_table->SocClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| D | dcn32_clk_mgr.c | 144 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn32_init_single_clock()
159 …struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entrie… in dcn32_init_clocks()
183 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn32_init_clocks()
188 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn32_init_clocks()
194 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn32_init_clocks()
199 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn32_init_clocks()
210 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz in dcn32_init_clocks()
212 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz in dcn32_init_clocks()
216 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950) in dcn32_init_clocks()
217 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950; in dcn32_init_clocks()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 97 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
133 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
139 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
144 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks()
150 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn3_init_clocks()
155 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
160 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
272 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_update_clocks()
370 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_min_memclk()
373 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn3_set_hard_min_memclk()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 171 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
172 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
182 …e.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfcl… in dcn32_build_wm_range_table_fpu()
184 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) in dcn32_build_wm_range_table_fpu()
185 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; in dcn32_build_wm_range_table_fpu()
223 …params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memcl… in dcn32_build_wm_range_table_fpu()
225 …params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memcl… in dcn32_build_wm_range_table_fpu()
227 …params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memcl… in dcn32_build_wm_range_table_fpu()
229 …params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memcl… in dcn32_build_wm_range_table_fpu()
1870 dcfclk = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
[all …]
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| /linux-6.1.9/drivers/clk/hisilicon/ |
| D | clk.c | 31 struct clk **clk_table; in hisi_clk_alloc() local
45 clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, in hisi_clk_alloc()
46 sizeof(*clk_table), in hisi_clk_alloc()
48 if (!clk_table) in hisi_clk_alloc()
51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
62 struct clk **clk_table; in hisi_clk_init() local
76 clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL); in hisi_clk_init()
77 if (!clk_table) in hisi_clk_init()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| D | dcn301_fpu.c | 327 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn301_update_bw_bounding_box() local
341 ASSERT(clk_table->num_entries); in dcn301_update_bw_bounding_box()
342 for (i = 0; i < clk_table->num_entries; i++) { in dcn301_update_bw_bounding_box()
345 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn301_update_bw_bounding_box()
352 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn301_update_bw_bounding_box()
353 s[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn301_update_bw_bounding_box()
354 s[i].socclk_mhz = clk_table->entries[i].socclk_mhz; in dcn301_update_bw_bounding_box()
355 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn301_update_bw_bounding_box()
368 if (clk_table->num_entries) { in dcn301_update_bw_bounding_box()
369 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_clk_mgr.c | 271 .clk_table = {
378 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn316_build_watermark_ranges()
381 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn316_build_watermark_ranges()
517 bw_params->clk_table.num_entries = j + 1; in dcn316_clk_mgr_helper_populate_bw_params()
528 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in dcn316_clk_mgr_helper_populate_bw_params()
531 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; in dcn316_clk_mgr_helper_populate_bw_params()
532 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn316_clk_mgr_helper_populate_bw_params()
533 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; in dcn316_clk_mgr_helper_populate_bw_params()
536 bw_params->clk_table.entries[i].wck_ratio = 2; in dcn316_clk_mgr_helper_populate_bw_params()
539 bw_params->clk_table.entries[i].wck_ratio = 4; in dcn316_clk_mgr_helper_populate_bw_params()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 335 .clk_table = {
442 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn31_build_watermark_ranges()
445 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn31_build_watermark_ranges()
580 bw_params->clk_table.num_entries = j + 1; in dcn31_clk_mgr_helper_populate_bw_params()
591 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in dcn31_clk_mgr_helper_populate_bw_params()
592 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; in dcn31_clk_mgr_helper_populate_bw_params()
593 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn31_clk_mgr_helper_populate_bw_params()
594 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; in dcn31_clk_mgr_helper_populate_bw_params()
597 bw_params->clk_table.entries[i].wck_ratio = 2; in dcn31_clk_mgr_helper_populate_bw_params()
600 bw_params->clk_table.entries[i].wck_ratio = 4; in dcn31_clk_mgr_helper_populate_bw_params()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | vangogh_ppt.c | 537 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in vangogh_get_dpm_clk_limited() local
539 if (!clk_table || clk_type >= SMU_CLK_COUNT) in vangogh_get_dpm_clk_limited()
544 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
546 *freq = clk_table->SocClocks[dpm_level]; in vangogh_get_dpm_clk_limited()
549 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
551 *freq = clk_table->VcnClocks[dpm_level].vclk; in vangogh_get_dpm_clk_limited()
554 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
556 *freq = clk_table->VcnClocks[dpm_level].dclk; in vangogh_get_dpm_clk_limited()
560 if (dpm_level >= clk_table->NumDfPstatesEnabled) in vangogh_get_dpm_clk_limited()
562 *freq = clk_table->DfPstateTable[dpm_level].memclk; in vangogh_get_dpm_clk_limited()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 477 …ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcf… in build_watermark_ranges()
479 …ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_… in build_watermark_ranges()
576 .clk_table = {
662 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
664 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in rn_clk_mgr_helper_populate_bw_params()
665 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
666 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
667 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; in rn_clk_mgr_helper_populate_bw_params()
668 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
669 bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table, in rn_clk_mgr_helper_populate_bw_params()
[all …]
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| /linux-6.1.9/drivers/clk/axis/ |
| D | clk-artpec6.c | 20 struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS]; member
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
107 clkdata->clk_data.clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
121 struct clk **clks = clkdata->clk_table; in artpec6_clkctrl_probe()
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