Searched refs:clk_state (Results 1 – 7 of 7) sorted by relevance
40 if (sched->clk_state == SLIM_CLK_ACTIVE) { in slim_ctrl_clk_pause()63 if (sched->clk_state == SLIM_CLK_PAUSED && ctrl->wakeup) in slim_ctrl_clk_pause()66 sched->clk_state = SLIM_CLK_ACTIVE; in slim_ctrl_clk_pause()73 if (ctrl->sched.clk_state == SLIM_CLK_PAUSED) { in slim_ctrl_clk_pause()89 sched->clk_state = SLIM_CLK_ENTERING_PAUSE; in slim_ctrl_clk_pause()112 sched->clk_state = SLIM_CLK_ACTIVE; in slim_ctrl_clk_pause()114 sched->clk_state = SLIM_CLK_PAUSED; in slim_ctrl_clk_pause()
120 if (ctrl->sched.clk_state == SLIM_CLK_ENTERING_PAUSE && in slim_do_transfer()128 if (ctrl->sched.clk_state != SLIM_CLK_ACTIVE) { in slim_do_transfer()130 ctrl->sched.clk_state, ret); in slim_do_transfer()
496 if (ctrl->sched.clk_state != SLIM_CLK_ACTIVE) { in slim_device_report_present()498 ctrl->sched.clk_state, ret); in slim_device_report_present()
178 enum slim_clk_state clk_state; member
288 enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info() local292 clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; in dce_clock_read_integrated_info()296 clk_state = DM_PP_CLOCKS_STATE_LOW; in dce_clock_read_integrated_info()300 clk_state = DM_PP_CLOCKS_STATE_NOMINAL; in dce_clock_read_integrated_info()304 clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; in dce_clock_read_integrated_info()308 clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info()316 clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = in dce_clock_read_integrated_info()
365 enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info() local369 clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; in dce_clock_read_integrated_info()373 clk_state = DM_PP_CLOCKS_STATE_LOW; in dce_clock_read_integrated_info()377 clk_state = DM_PP_CLOCKS_STATE_NOMINAL; in dce_clock_read_integrated_info()381 clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; in dce_clock_read_integrated_info()385 clk_state = DM_PP_CLOCKS_STATE_INVALID; in dce_clock_read_integrated_info()392 clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = in dce_clock_read_integrated_info()
166 enum s3c_nand_clk_state clk_state; member234 if (info->clk_state == CLOCK_ENABLE) { in s3c2410_nand_clk_set_state()242 info->clk_state = new_state; in s3c2410_nand_clk_set_state()