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Searched refs:bin_cl_size (Results 1 – 5 of 5) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/vc4/
Dvc4_trace.h56 TP_PROTO(struct drm_device *dev, u32 bin_cl_size, u32 shader_rec_size, u32 bo_count),
57 TP_ARGS(dev, bin_cl_size, shader_rec_size, bo_count),
61 __field(u32, bin_cl_size)
68 __entry->bin_cl_size = bin_cl_size;
75 __entry->bin_cl_size,
Dvc4_render_cl.c128 bool has_bin = args->bin_cl_size != 0; in emit_tile()
257 bool has_bin = args->bin_cl_size != 0; in vc4_create_rcl_bo()
599 bool has_bin = args->bin_cl_size != 0; in vc4_get_rcl()
Dvc4_gem.c849 uint32_t shader_rec_offset = roundup(bin_offset + args->bin_cl_size, in vc4_get_bcl()
857 if (shader_rec_offset < args->bin_cl_size || in vc4_get_bcl()
890 args->bin_cl_size)) { in vc4_get_bcl()
1172 trace_vc4_submit_cl_ioctl(dev, args->bin_cl_size, in vc4_submit_cl_ioctl()
1249 if (exec->args->bin_cl_size != 0) { in vc4_submit_cl_ioctl()
Dvc4_validate.c224 if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 1)) { in validate_flush()
253 if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 2)) { in validate_increment_semaphore()
494 uint32_t len = exec->args->bin_cl_size; in vc4_validate_bin_cl()
/linux-6.1.9/include/uapi/drm/
Dvc4_drm.h130 __u32 bin_cl_size; member