1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * R8A779A0 processor support - PFC hardware block.
4  *
5  * Copyright (C) 2020 Renesas Electronics Corp.
6  *
7  * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
8  */
9 
10 #include <linux/errno.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 
14 #include "sh_pfc.h"
15 
16 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
17 
18 #define CPU_ALL_GP(fn, sfx)	\
19 	PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS),	\
20 	PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
21 	PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
22 	PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
23 	PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
24 	PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
25 	PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
26 	PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
27 	PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
28 	PORT_GP_CFG_1(0, 23, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
29 	PORT_GP_CFG_1(0, 24, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
30 	PORT_GP_CFG_1(0, 25, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
31 	PORT_GP_CFG_1(0, 26, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
32 	PORT_GP_CFG_1(0, 27, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
33 	PORT_GP_CFG_31(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
34 	PORT_GP_CFG_2(2, fn, sfx, CFG_FLAGS),					\
35 	PORT_GP_CFG_1(2, 2, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
36 	PORT_GP_CFG_1(2, 3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
37 	PORT_GP_CFG_1(2, 4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
38 	PORT_GP_CFG_1(2, 5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
39 	PORT_GP_CFG_1(2, 6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
40 	PORT_GP_CFG_1(2, 7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
41 	PORT_GP_CFG_1(2, 8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
42 	PORT_GP_CFG_1(2, 9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
43 	PORT_GP_CFG_1(2, 10, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
44 	PORT_GP_CFG_1(2, 11, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
45 	PORT_GP_CFG_1(2, 12, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
46 	PORT_GP_CFG_1(2, 13, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
47 	PORT_GP_CFG_1(2, 14, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
48 	PORT_GP_CFG_1(2, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),	\
49 	PORT_GP_CFG_1(2, 16, fn, sfx, CFG_FLAGS),	\
50 	PORT_GP_CFG_1(2, 17, fn, sfx, CFG_FLAGS),	\
51 	PORT_GP_CFG_1(2, 18, fn, sfx, CFG_FLAGS),	\
52 	PORT_GP_CFG_1(2, 19, fn, sfx, CFG_FLAGS),	\
53 	PORT_GP_CFG_1(2, 20, fn, sfx, CFG_FLAGS),	\
54 	PORT_GP_CFG_1(2, 21, fn, sfx, CFG_FLAGS),	\
55 	PORT_GP_CFG_1(2, 22, fn, sfx, CFG_FLAGS),	\
56 	PORT_GP_CFG_1(2, 23, fn, sfx, CFG_FLAGS),	\
57 	PORT_GP_CFG_1(2, 24, fn, sfx, CFG_FLAGS),	\
58 	PORT_GP_CFG_17(3, fn, sfx, CFG_FLAGS),	\
59 	PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
60 	PORT_GP_CFG_1(4, 18, fn, sfx, CFG_FLAGS),	\
61 	PORT_GP_CFG_1(4, 19, fn, sfx, CFG_FLAGS),	\
62 	PORT_GP_CFG_1(4, 20, fn, sfx, CFG_FLAGS),	\
63 	PORT_GP_CFG_1(4, 21, fn, sfx, CFG_FLAGS),	\
64 	PORT_GP_CFG_1(4, 22, fn, sfx, CFG_FLAGS),	\
65 	PORT_GP_CFG_1(4, 23, fn, sfx, CFG_FLAGS),	\
66 	PORT_GP_CFG_1(4, 24, fn, sfx, CFG_FLAGS),	\
67 	PORT_GP_CFG_1(4, 25, fn, sfx, CFG_FLAGS),	\
68 	PORT_GP_CFG_1(4, 26, fn, sfx, CFG_FLAGS),	\
69 	PORT_GP_CFG_18(5, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
70 	PORT_GP_CFG_1(5, 18, fn, sfx, CFG_FLAGS),	\
71 	PORT_GP_CFG_1(5, 19, fn, sfx, CFG_FLAGS),	\
72 	PORT_GP_CFG_1(5, 20, fn, sfx, CFG_FLAGS),	\
73 	PORT_GP_CFG_18(6, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
74 	PORT_GP_CFG_1(6, 18, fn, sfx, CFG_FLAGS),	\
75 	PORT_GP_CFG_1(6, 19, fn, sfx, CFG_FLAGS),	\
76 	PORT_GP_CFG_1(6, 20, fn, sfx, CFG_FLAGS),	\
77 	PORT_GP_CFG_18(7, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
78 	PORT_GP_CFG_1(7, 18, fn, sfx, CFG_FLAGS),	\
79 	PORT_GP_CFG_1(7, 19, fn, sfx, CFG_FLAGS),	\
80 	PORT_GP_CFG_1(7, 20, fn, sfx, CFG_FLAGS),	\
81 	PORT_GP_CFG_18(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
82 	PORT_GP_CFG_1(8, 18, fn, sfx, CFG_FLAGS),	\
83 	PORT_GP_CFG_1(8, 19, fn, sfx, CFG_FLAGS),	\
84 	PORT_GP_CFG_1(8, 20, fn, sfx, CFG_FLAGS),	\
85 	PORT_GP_CFG_18(9, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_25_33),\
86 	PORT_GP_CFG_1(9, 18, fn, sfx, CFG_FLAGS),	\
87 	PORT_GP_CFG_1(9, 19, fn, sfx, CFG_FLAGS),	\
88 	PORT_GP_CFG_1(9, 20, fn, sfx, CFG_FLAGS)
89 
90 #define CPU_ALL_NOGP(fn)									\
91 	PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),		\
92 	PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),			\
93 	PIN_NOGP_CFG(DCUTRST_N_LPDRST_N, "DCUTRST#_LPDRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),	\
94 	PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),		\
95 	PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),			\
96 	PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
97 
98 /*
99  * F_() : just information
100  * FM() : macro for FN_xxx / xxx_MARK
101  */
102 
103 /* GPSR0 */
104 #define GPSR0_27	FM(MMC_D7)
105 #define GPSR0_26	FM(MMC_D6)
106 #define GPSR0_25	FM(MMC_D5)
107 #define GPSR0_24	FM(MMC_D4)
108 #define GPSR0_23	FM(MMC_SD_CLK)
109 #define GPSR0_22	FM(MMC_SD_D3)
110 #define GPSR0_21	FM(MMC_SD_D2)
111 #define GPSR0_20	FM(MMC_SD_D1)
112 #define GPSR0_19	FM(MMC_SD_D0)
113 #define GPSR0_18	FM(MMC_SD_CMD)
114 #define GPSR0_17	FM(MMC_DS)
115 #define GPSR0_16	FM(SD_CD)
116 #define GPSR0_15	FM(SD_WP)
117 #define GPSR0_14	FM(RPC_INT_N)
118 #define GPSR0_13	FM(RPC_WP_N)
119 #define GPSR0_12	FM(RPC_RESET_N)
120 #define GPSR0_11	FM(QSPI1_SSL)
121 #define GPSR0_10	FM(QSPI1_IO3)
122 #define GPSR0_9		FM(QSPI1_IO2)
123 #define GPSR0_8		FM(QSPI1_MISO_IO1)
124 #define GPSR0_7		FM(QSPI1_MOSI_IO0)
125 #define GPSR0_6		FM(QSPI1_SPCLK)
126 #define GPSR0_5		FM(QSPI0_SSL)
127 #define GPSR0_4		FM(QSPI0_IO3)
128 #define GPSR0_3		FM(QSPI0_IO2)
129 #define GPSR0_2		FM(QSPI0_MISO_IO1)
130 #define GPSR0_1		FM(QSPI0_MOSI_IO0)
131 #define GPSR0_0		FM(QSPI0_SPCLK)
132 
133 /* GPSR1 */
134 #define GPSR1_30	F_(GP1_30,	IP3SR1_27_24)
135 #define GPSR1_29	F_(GP1_29,	IP3SR1_23_20)
136 #define GPSR1_28	F_(GP1_28,	IP3SR1_19_16)
137 #define GPSR1_27	F_(IRQ3,	IP3SR1_15_12)
138 #define GPSR1_26	F_(IRQ2,	IP3SR1_11_8)
139 #define GPSR1_25	F_(IRQ1,	IP3SR1_7_4)
140 #define GPSR1_24	F_(IRQ0,	IP3SR1_3_0)
141 #define GPSR1_23	F_(MSIOF2_SS2,	IP2SR1_31_28)
142 #define GPSR1_22	F_(MSIOF2_SS1,	IP2SR1_27_24)
143 #define GPSR1_21	F_(MSIOF2_SYNC,	IP2SR1_23_20)
144 #define GPSR1_20	F_(MSIOF2_SCK,	IP2SR1_19_16)
145 #define GPSR1_19	F_(MSIOF2_TXD,	IP2SR1_15_12)
146 #define GPSR1_18	F_(MSIOF2_RXD,	IP2SR1_11_8)
147 #define GPSR1_17	F_(MSIOF1_SS2,	IP2SR1_7_4)
148 #define GPSR1_16	F_(MSIOF1_SS1,	IP2SR1_3_0)
149 #define GPSR1_15	F_(MSIOF1_SYNC,	IP1SR1_31_28)
150 #define GPSR1_14	F_(MSIOF1_SCK,	IP1SR1_27_24)
151 #define GPSR1_13	F_(MSIOF1_TXD,	IP1SR1_23_20)
152 #define GPSR1_12	F_(MSIOF1_RXD,	IP1SR1_19_16)
153 #define GPSR1_11	F_(MSIOF0_SS2,	IP1SR1_15_12)
154 #define GPSR1_10	F_(MSIOF0_SS1,	IP1SR1_11_8)
155 #define GPSR1_9		F_(MSIOF0_SYNC,	IP1SR1_7_4)
156 #define GPSR1_8		F_(MSIOF0_SCK,	IP1SR1_3_0)
157 #define GPSR1_7		F_(MSIOF0_TXD,	IP0SR1_31_28)
158 #define GPSR1_6		F_(MSIOF0_RXD,	IP0SR1_27_24)
159 #define GPSR1_5		F_(HTX0,	IP0SR1_23_20)
160 #define GPSR1_4		F_(HCTS0_N,	IP0SR1_19_16)
161 #define GPSR1_3		F_(HRTS0_N,	IP0SR1_15_12)
162 #define GPSR1_2		F_(HSCK0,	IP0SR1_11_8)
163 #define GPSR1_1		F_(HRX0,	IP0SR1_7_4)
164 #define GPSR1_0		F_(SCIF_CLK,	IP0SR1_3_0)
165 
166 /* GPSR2 */
167 #define GPSR2_24	FM(TCLK2_A)
168 #define GPSR2_23	F_(TCLK1_A,		IP2SR2_31_28)
169 #define GPSR2_22	F_(TPU0TO1,		IP2SR2_27_24)
170 #define GPSR2_21	F_(TPU0TO0,		IP2SR2_23_20)
171 #define GPSR2_20	F_(CLK_EXTFXR,		IP2SR2_19_16)
172 #define GPSR2_19	F_(RXDB_EXTFXR,		IP2SR2_15_12)
173 #define GPSR2_18	F_(FXR_TXDB,		IP2SR2_11_8)
174 #define GPSR2_17	F_(RXDA_EXTFXR_A,	IP2SR2_7_4)
175 #define GPSR2_16	F_(FXR_TXDA_A,		IP2SR2_3_0)
176 #define GPSR2_15	F_(GP2_15,		IP1SR2_31_28)
177 #define GPSR2_14	F_(GP2_14,		IP1SR2_27_24)
178 #define GPSR2_13	F_(GP2_13,		IP1SR2_23_20)
179 #define GPSR2_12	F_(GP2_12,		IP1SR2_19_16)
180 #define GPSR2_11	F_(GP2_11,		IP1SR2_15_12)
181 #define GPSR2_10	F_(GP2_10,		IP1SR2_11_8)
182 #define GPSR2_9		F_(GP2_09,		IP1SR2_7_4)
183 #define GPSR2_8		F_(GP2_08,		IP1SR2_3_0)
184 #define GPSR2_7		F_(GP2_07,		IP0SR2_31_28)
185 #define GPSR2_6		F_(GP2_06,		IP0SR2_27_24)
186 #define GPSR2_5		F_(GP2_05,		IP0SR2_23_20)
187 #define GPSR2_4		F_(GP2_04,		IP0SR2_19_16)
188 #define GPSR2_3		F_(GP2_03,		IP0SR2_15_12)
189 #define GPSR2_2		F_(GP2_02,		IP0SR2_11_8)
190 #define GPSR2_1		F_(IPC_CLKOUT,		IP0SR2_7_4)
191 #define GPSR2_0		F_(IPC_CLKIN,		IP0SR2_3_0)
192 
193 /* GPSR3 */
194 #define GPSR3_16	FM(CANFD7_RX)
195 #define GPSR3_15	FM(CANFD7_TX)
196 #define GPSR3_14	FM(CANFD6_RX)
197 #define GPSR3_13	F_(CANFD6_TX,	IP1SR3_23_20)
198 #define GPSR3_12	F_(CANFD5_RX,	IP1SR3_19_16)
199 #define GPSR3_11	F_(CANFD5_TX,	IP1SR3_15_12)
200 #define GPSR3_10	F_(CANFD4_RX,	IP1SR3_11_8)
201 #define GPSR3_9		F_(CANFD4_TX,	IP1SR3_7_4)
202 #define GPSR3_8		F_(CANFD3_RX,	IP1SR3_3_0)
203 #define GPSR3_7		F_(CANFD3_TX,	IP0SR3_31_28)
204 #define GPSR3_6		F_(CANFD2_RX,	IP0SR3_27_24)
205 #define GPSR3_5		F_(CANFD2_TX,	IP0SR3_23_20)
206 #define GPSR3_4		FM(CANFD1_RX)
207 #define GPSR3_3		FM(CANFD1_TX)
208 #define GPSR3_2		F_(CANFD0_RX,	IP0SR3_11_8)
209 #define GPSR3_1		F_(CANFD0_TX,	IP0SR3_7_4)
210 #define GPSR3_0		FM(CAN_CLK)
211 
212 /* GPSR4 */
213 #define GPSR4_26	FM(AVS1)
214 #define GPSR4_25	FM(AVS0)
215 #define GPSR4_24	FM(PCIE3_CLKREQ_N)
216 #define GPSR4_23	FM(PCIE2_CLKREQ_N)
217 #define GPSR4_22	FM(PCIE1_CLKREQ_N)
218 #define GPSR4_21	FM(PCIE0_CLKREQ_N)
219 #define GPSR4_20	F_(AVB0_AVTP_PPS,	IP2SR4_19_16)
220 #define GPSR4_19	F_(AVB0_AVTP_CAPTURE,	IP2SR4_15_12)
221 #define GPSR4_18	F_(AVB0_AVTP_MATCH,	IP2SR4_11_8)
222 #define GPSR4_17	F_(AVB0_LINK,		IP2SR4_7_4)
223 #define GPSR4_16	FM(AVB0_PHY_INT)
224 #define GPSR4_15	F_(AVB0_MAGIC,		IP1SR4_31_28)
225 #define GPSR4_14	F_(AVB0_MDC,		IP1SR4_27_24)
226 #define GPSR4_13	F_(AVB0_MDIO,		IP1SR4_23_20)
227 #define GPSR4_12	F_(AVB0_TXCREFCLK,	IP1SR4_19_16)
228 #define GPSR4_11	F_(AVB0_TD3,		IP1SR4_15_12)
229 #define GPSR4_10	F_(AVB0_TD2,		IP1SR4_11_8)
230 #define GPSR4_9		F_(AVB0_TD1,		IP1SR4_7_4)
231 #define GPSR4_8		F_(AVB0_TD0,		IP1SR4_3_0)
232 #define GPSR4_7		F_(AVB0_TXC,		IP0SR4_31_28)
233 #define GPSR4_6		F_(AVB0_TX_CTL,		IP0SR4_27_24)
234 #define GPSR4_5		F_(AVB0_RD3,		IP0SR4_23_20)
235 #define GPSR4_4		F_(AVB0_RD2,		IP0SR4_19_16)
236 #define GPSR4_3		F_(AVB0_RD1,		IP0SR4_15_12)
237 #define GPSR4_2		F_(AVB0_RD0,		IP0SR4_11_8)
238 #define GPSR4_1		F_(AVB0_RXC,		IP0SR4_7_4)
239 #define GPSR4_0		F_(AVB0_RX_CTL,		IP0SR4_3_0)
240 
241 /* GPSR5 */
242 #define GPSR5_20	F_(AVB1_AVTP_PPS,	IP2SR5_19_16)
243 #define GPSR5_19	F_(AVB1_AVTP_CAPTURE,	IP2SR5_15_12)
244 #define GPSR5_18	F_(AVB1_AVTP_MATCH,	IP2SR5_11_8)
245 #define GPSR5_17	F_(AVB1_LINK,		IP2SR5_7_4)
246 #define GPSR5_16	FM(AVB1_PHY_INT)
247 #define GPSR5_15	F_(AVB1_MAGIC,		IP1SR5_31_28)
248 #define GPSR5_14	F_(AVB1_MDC,		IP1SR5_27_24)
249 #define GPSR5_13	F_(AVB1_MDIO,		IP1SR5_23_20)
250 #define GPSR5_12	F_(AVB1_TXCREFCLK,	IP1SR5_19_16)
251 #define GPSR5_11	F_(AVB1_TD3,		IP1SR5_15_12)
252 #define GPSR5_10	F_(AVB1_TD2,		IP1SR5_11_8)
253 #define GPSR5_9		F_(AVB1_TD1,		IP1SR5_7_4)
254 #define GPSR5_8		F_(AVB1_TD0,		IP1SR5_3_0)
255 #define GPSR5_7		F_(AVB1_TXC,		IP0SR5_31_28)
256 #define GPSR5_6		F_(AVB1_TX_CTL,		IP0SR5_27_24)
257 #define GPSR5_5		F_(AVB1_RD3,		IP0SR5_23_20)
258 #define GPSR5_4		F_(AVB1_RD2,		IP0SR5_19_16)
259 #define GPSR5_3		F_(AVB1_RD1,		IP0SR5_15_12)
260 #define GPSR5_2		F_(AVB1_RD0,		IP0SR5_11_8)
261 #define GPSR5_1		F_(AVB1_RXC,		IP0SR5_7_4)
262 #define GPSR5_0		F_(AVB1_RX_CTL,		IP0SR5_3_0)
263 
264 /* GPSR6 */
265 #define GPSR6_20	FM(AVB2_AVTP_PPS)
266 #define GPSR6_19	FM(AVB2_AVTP_CAPTURE)
267 #define GPSR6_18	FM(AVB2_AVTP_MATCH)
268 #define GPSR6_17	FM(AVB2_LINK)
269 #define GPSR6_16	FM(AVB2_PHY_INT)
270 #define GPSR6_15	FM(AVB2_MAGIC)
271 #define GPSR6_14	FM(AVB2_MDC)
272 #define GPSR6_13	FM(AVB2_MDIO)
273 #define GPSR6_12	FM(AVB2_TXCREFCLK)
274 #define GPSR6_11	FM(AVB2_TD3)
275 #define GPSR6_10	FM(AVB2_TD2)
276 #define GPSR6_9		FM(AVB2_TD1)
277 #define GPSR6_8		FM(AVB2_TD0)
278 #define GPSR6_7		FM(AVB2_TXC)
279 #define GPSR6_6		FM(AVB2_TX_CTL)
280 #define GPSR6_5		FM(AVB2_RD3)
281 #define GPSR6_4		FM(AVB2_RD2)
282 #define GPSR6_3		FM(AVB2_RD1)
283 #define GPSR6_2		FM(AVB2_RD0)
284 #define GPSR6_1		FM(AVB2_RXC)
285 #define GPSR6_0		FM(AVB2_RX_CTL)
286 
287 /* GPSR7 */
288 #define GPSR7_20	FM(AVB3_AVTP_PPS)
289 #define GPSR7_19	FM(AVB3_AVTP_CAPTURE)
290 #define GPSR7_18	FM(AVB3_AVTP_MATCH)
291 #define GPSR7_17	FM(AVB3_LINK)
292 #define GPSR7_16	FM(AVB3_PHY_INT)
293 #define GPSR7_15	FM(AVB3_MAGIC)
294 #define GPSR7_14	FM(AVB3_MDC)
295 #define GPSR7_13	FM(AVB3_MDIO)
296 #define GPSR7_12	FM(AVB3_TXCREFCLK)
297 #define GPSR7_11	FM(AVB3_TD3)
298 #define GPSR7_10	FM(AVB3_TD2)
299 #define GPSR7_9		FM(AVB3_TD1)
300 #define GPSR7_8		FM(AVB3_TD0)
301 #define GPSR7_7		FM(AVB3_TXC)
302 #define GPSR7_6		FM(AVB3_TX_CTL)
303 #define GPSR7_5		FM(AVB3_RD3)
304 #define GPSR7_4		FM(AVB3_RD2)
305 #define GPSR7_3		FM(AVB3_RD1)
306 #define GPSR7_2		FM(AVB3_RD0)
307 #define GPSR7_1		FM(AVB3_RXC)
308 #define GPSR7_0		FM(AVB3_RX_CTL)
309 
310 /* GPSR8 */
311 #define GPSR8_20	FM(AVB4_AVTP_PPS)
312 #define GPSR8_19	FM(AVB4_AVTP_CAPTURE)
313 #define GPSR8_18	FM(AVB4_AVTP_MATCH)
314 #define GPSR8_17	FM(AVB4_LINK)
315 #define GPSR8_16	FM(AVB4_PHY_INT)
316 #define GPSR8_15	FM(AVB4_MAGIC)
317 #define GPSR8_14	FM(AVB4_MDC)
318 #define GPSR8_13	FM(AVB4_MDIO)
319 #define GPSR8_12	FM(AVB4_TXCREFCLK)
320 #define GPSR8_11	FM(AVB4_TD3)
321 #define GPSR8_10	FM(AVB4_TD2)
322 #define GPSR8_9		FM(AVB4_TD1)
323 #define GPSR8_8		FM(AVB4_TD0)
324 #define GPSR8_7		FM(AVB4_TXC)
325 #define GPSR8_6		FM(AVB4_TX_CTL)
326 #define GPSR8_5		FM(AVB4_RD3)
327 #define GPSR8_4		FM(AVB4_RD2)
328 #define GPSR8_3		FM(AVB4_RD1)
329 #define GPSR8_2		FM(AVB4_RD0)
330 #define GPSR8_1		FM(AVB4_RXC)
331 #define GPSR8_0		FM(AVB4_RX_CTL)
332 
333 /* GPSR9 */
334 #define GPSR9_20	FM(AVB5_AVTP_PPS)
335 #define GPSR9_19	FM(AVB5_AVTP_CAPTURE)
336 #define GPSR9_18	FM(AVB5_AVTP_MATCH)
337 #define GPSR9_17	FM(AVB5_LINK)
338 #define GPSR9_16	FM(AVB5_PHY_INT)
339 #define GPSR9_15	FM(AVB5_MAGIC)
340 #define GPSR9_14	FM(AVB5_MDC)
341 #define GPSR9_13	FM(AVB5_MDIO)
342 #define GPSR9_12	FM(AVB5_TXCREFCLK)
343 #define GPSR9_11	FM(AVB5_TD3)
344 #define GPSR9_10	FM(AVB5_TD2)
345 #define GPSR9_9		FM(AVB5_TD1)
346 #define GPSR9_8		FM(AVB5_TD0)
347 #define GPSR9_7		FM(AVB5_TXC)
348 #define GPSR9_6		FM(AVB5_TX_CTL)
349 #define GPSR9_5		FM(AVB5_RD3)
350 #define GPSR9_4		FM(AVB5_RD2)
351 #define GPSR9_3		FM(AVB5_RD1)
352 #define GPSR9_2		FM(AVB5_RD0)
353 #define GPSR9_1		FM(AVB5_RXC)
354 #define GPSR9_0		FM(AVB5_RX_CTL)
355 
356 /* IP0SR1 */		/* 0 */		/* 1 */		/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
357 #define IP0SR1_3_0	FM(SCIF_CLK)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(A0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP0SR1_7_4	FM(HRX0)	FM(RX0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(A1)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP0SR1_11_8	FM(HSCK0)	FM(SCK0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(A2)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP0SR1_15_12	FM(HRTS0_N)	FM(RTS0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(A3)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP0SR1_19_16	FM(HCTS0_N)	FM(CTS0_N)	F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(A4)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP0SR1_23_20	FM(HTX0)	FM(TX0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(A5)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP0SR1_27_24	FM(MSIOF0_RXD)	F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(DU_DR2)	FM(A6)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP0SR1_31_28	FM(MSIOF0_TXD)	F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(DU_DR3)	FM(A7)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 /* IP1SR1 */		/* 0 */		/* 1 */		/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
366 #define IP1SR1_3_0	FM(MSIOF0_SCK)	F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(DU_DR4)	FM(A8)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP1SR1_7_4	FM(MSIOF0_SYNC)	F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(DU_DR5)	FM(A9)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP1SR1_11_8	FM(MSIOF0_SS1)	F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(DU_DR6)	FM(A10)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP1SR1_15_12	FM(MSIOF0_SS2)	F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(DU_DR7)	FM(A11)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP1SR1_19_16	FM(MSIOF1_RXD)	F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(DU_DG2)	FM(A12)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP1SR1_23_20	FM(MSIOF1_TXD)	FM(HRX3)	FM(SCK3)	F_(0, 0)	FM(DU_DG3)	FM(A13)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP1SR1_27_24	FM(MSIOF1_SCK)	FM(HSCK3)	FM(CTS3_N)	F_(0, 0)	FM(DU_DG4)	FM(A14)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP1SR1_31_28	FM(MSIOF1_SYNC)	FM(HRTS3_N)	FM(RTS3_N)	F_(0, 0)	FM(DU_DG5)	FM(A15)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 /* IP2SR1 */		/* 0 */		/* 1 */		/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
375 #define IP2SR1_3_0	FM(MSIOF1_SS1)	FM(HCTS3_N)	FM(RX3)		F_(0, 0)	FM(DU_DG6)	FM(A16)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376 #define IP2SR1_7_4	FM(MSIOF1_SS2)	FM(HTX3)	FM(TX3)		F_(0, 0)	FM(DU_DG7)	FM(A17)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP2SR1_11_8	FM(MSIOF2_RXD)	FM(HSCK1)	FM(SCK1)	F_(0, 0)	FM(DU_DB2)	FM(A18)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP2SR1_15_12	FM(MSIOF2_TXD)	FM(HCTS1_N)	FM(CTS1_N)	F_(0, 0)	FM(DU_DB3)	FM(A19)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP2SR1_19_16	FM(MSIOF2_SCK)	FM(HRTS1_N)	FM(RTS1_N)	F_(0, 0)	FM(DU_DB4)	FM(A20)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP2SR1_23_20	FM(MSIOF2_SYNC)	FM(HRX1)	FM(RX1_A)	F_(0, 0)	FM(DU_DB5)	FM(A21)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP2SR1_27_24	FM(MSIOF2_SS1)	FM(HTX1)	FM(TX1_A)	F_(0, 0)	FM(DU_DB6)	FM(A22)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP2SR1_31_28	FM(MSIOF2_SS2)	FM(TCLK1_B)	F_(0, 0)	F_(0, 0)	FM(DU_DB7)	FM(A23)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383 
384 /* IP3SR1 */		/* 0 */			/* 1 */		/* 2 */		/* 3 */		/* 4 */			/* 5 */		/* 6 - F */
385 #define IP3SR1_3_0	FM(IRQ0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(DU_DOTCLKOUT)	FM(A24)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP3SR1_7_4	FM(IRQ1)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(DU_HSYNC)		FM(A25)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP3SR1_11_8	FM(IRQ2)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(DU_VSYNC)		FM(CS1_N_A26)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP3SR1_15_12	FM(IRQ3)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(DU_ODDF_DISP_CDE)	FM(CS0_N)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP3SR1_19_16	FM(GP1_28)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(D0)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP3SR1_23_20	FM(GP1_29)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(D1)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP3SR1_27_24	FM(GP1_30)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)		FM(D2)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 
393 /* IP0SR2 */		/* 0 */			/* 1 */			/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
394 #define IP0SR2_3_0	FM(IPC_CLKIN)		FM(IPC_CLKEN_IN)	F_(0, 0)	F_(0, 0)	FM(DU_DOTCLKIN)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP0SR2_7_4	FM(IPC_CLKOUT)		FM(IPC_CLKEN_OUT)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP0SR2_11_8	FM(GP2_02)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(D3)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP0SR2_15_12	FM(GP2_03)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(D4)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP0SR2_19_16	FM(GP2_04)		F_(0, 0)		FM(MSIOF4_RXD)	F_(0, 0)	F_(0, 0)	FM(D5)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP0SR2_23_20	FM(GP2_05)		FM(HSCK2)		FM(MSIOF4_TXD)	FM(SCK4)	F_(0, 0)	FM(D6)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP0SR2_27_24	FM(GP2_06)		FM(HCTS2_N)		FM(MSIOF4_SCK)	FM(CTS4_N)	F_(0, 0)	FM(D7)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP0SR2_31_28	FM(GP2_07)		FM(HRTS2_N)		FM(MSIOF4_SYNC)	FM(RTS4_N)	F_(0, 0)	FM(D8)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 /* IP1SR2 */		/* 0 */			/* 1 */			/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
403 #define IP1SR2_3_0	FM(GP2_08)		FM(HRX2)		FM(MSIOF4_SS1)	FM(RX4)		F_(0, 0)	FM(D9)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP1SR2_7_4	FM(GP2_09)		FM(HTX2)		FM(MSIOF4_SS2)	FM(TX4)		F_(0, 0)	FM(D10)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405 #define IP1SR2_11_8	FM(GP2_10)		FM(TCLK2_B)		FM(MSIOF5_RXD)	F_(0, 0)	F_(0, 0)	FM(D11)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
406 #define IP1SR2_15_12	FM(GP2_11)		FM(TCLK3)		FM(MSIOF5_TXD)	F_(0, 0)	F_(0, 0)	FM(D12)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407 #define IP1SR2_19_16	FM(GP2_12)		FM(TCLK4)		FM(MSIOF5_SCK)	F_(0, 0)	F_(0, 0)	FM(D13)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
408 #define IP1SR2_23_20	FM(GP2_13)		F_(0, 0)		FM(MSIOF5_SYNC)	F_(0, 0)	F_(0, 0)	FM(D14)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
409 #define IP1SR2_27_24	FM(GP2_14)		FM(IRQ4)		FM(MSIOF5_SS1)	F_(0, 0)	F_(0, 0)	FM(D15)		F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP1SR2_31_28	FM(GP2_15)		FM(IRQ5)		FM(MSIOF5_SS2)	FM(CPG_CPCKOUT)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411 /* IP2SR2 */		/* 0 */			/* 1 */			/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
412 #define IP2SR2_3_0	FM(FXR_TXDA_A)		FM(MSIOF3_SS1)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
413 #define IP2SR2_7_4	FM(RXDA_EXTFXR_A)	FM(MSIOF3_SS2)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(BS_N)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
414 #define IP2SR2_11_8	FM(FXR_TXDB)		FM(MSIOF3_RXD)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(RD_N)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
415 #define IP2SR2_15_12	FM(RXDB_EXTFXR)		FM(MSIOF3_TXD)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(WE0_N)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
416 #define IP2SR2_19_16	FM(CLK_EXTFXR)		FM(MSIOF3_SCK)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(WE1_N)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
417 #define IP2SR2_23_20	FM(TPU0TO0)		FM(MSIOF3_SYNC)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(RD_WR_N)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
418 #define IP2SR2_27_24	FM(TPU0TO1)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(CLKOUT)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
419 #define IP2SR2_31_28	FM(TCLK1_A)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	FM(EX_WAIT0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
420 
421 /* IP0SR3 */		/* 0 */		/* 1 */			/* 2 */		/* 3 */			/* 4 */		/* 5 */		/* 6 - F */
422 #define IP0SR3_7_4	FM(CANFD0_TX)	FM(FXR_TXDA_B)		FM(TX1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
423 #define IP0SR3_11_8	FM(CANFD0_RX)	FM(RXDA_EXTFXR_B)	FM(RX1_B)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
424 #define IP0SR3_23_20	FM(CANFD2_TX)	FM(TPU0TO2)		FM(PWM0)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
425 #define IP0SR3_27_24	FM(CANFD2_RX)	FM(TPU0TO3)		FM(PWM1)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
426 #define IP0SR3_31_28	FM(CANFD3_TX)	F_(0, 0)		FM(PWM2)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
427 /* IP1SR3 */		/* 0 */		/* 1 */			/* 2 */		/* 3 */			/* 4 */		/* 5 */		/* 6 - F */
428 #define IP1SR3_3_0	FM(CANFD3_RX)	F_(0, 0)		FM(PWM3)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
429 #define IP1SR3_7_4	FM(CANFD4_TX)	F_(0, 0)		FM(PWM4)	FM(FXR_CLKOUT1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
430 #define IP1SR3_11_8	FM(CANFD4_RX)	F_(0, 0)		F_(0, 0)	FM(FXR_CLKOUT2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
431 #define IP1SR3_15_12	FM(CANFD5_TX)	F_(0, 0)		F_(0, 0)	FM(FXR_TXENA_N)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
432 #define IP1SR3_19_16	FM(CANFD5_RX)	F_(0, 0)		F_(0, 0)	FM(FXR_TXENB_N)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
433 #define IP1SR3_23_20	FM(CANFD6_TX)	F_(0, 0)		F_(0, 0)	FM(STPWT_EXTFXR)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
434 
435 /* IP0SR4 */		/* 0 */		/* 1 */			/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
436 #define IP0SR4_3_0	FM(AVB0_RX_CTL)	FM(AVB0_MII_RX_DV)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
437 #define IP0SR4_7_4	FM(AVB0_RXC)	FM(AVB0_MII_RXC)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
438 #define IP0SR4_11_8	FM(AVB0_RD0)	FM(AVB0_MII_RD0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
439 #define IP0SR4_15_12	FM(AVB0_RD1)	FM(AVB0_MII_RD1)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
440 #define IP0SR4_19_16	FM(AVB0_RD2)	FM(AVB0_MII_RD2)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
441 #define IP0SR4_23_20	FM(AVB0_RD3)	FM(AVB0_MII_RD3)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
442 #define IP0SR4_27_24	FM(AVB0_TX_CTL)	FM(AVB0_MII_TX_EN)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
443 #define IP0SR4_31_28	FM(AVB0_TXC)	FM(AVB0_MII_TXC)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
444 /* IP1SR4 */		/* 0 */			/* 1 */			/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
445 #define IP1SR4_3_0	FM(AVB0_TD0)		FM(AVB0_MII_TD0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
446 #define IP1SR4_7_4	FM(AVB0_TD1)		FM(AVB0_MII_TD1)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
447 #define IP1SR4_11_8	FM(AVB0_TD2)		FM(AVB0_MII_TD2)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
448 #define IP1SR4_15_12	FM(AVB0_TD3)		FM(AVB0_MII_TD3)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
449 #define IP1SR4_19_16	FM(AVB0_TXCREFCLK)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
450 #define IP1SR4_23_20	FM(AVB0_MDIO)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
451 #define IP1SR4_27_24	FM(AVB0_MDC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
452 #define IP1SR4_31_28	FM(AVB0_MAGIC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
453 /* IP2SR4 */		/* 0 */			/* 1 */			/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
454 #define IP2SR4_7_4	FM(AVB0_LINK)		FM(AVB0_MII_TX_ER)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
455 #define IP2SR4_11_8	FM(AVB0_AVTP_MATCH)	FM(AVB0_MII_RX_ER)	FM(CC5_OSCOUT)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
456 #define IP2SR4_15_12	FM(AVB0_AVTP_CAPTURE)	FM(AVB0_MII_CRS)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
457 #define IP2SR4_19_16	FM(AVB0_AVTP_PPS)	FM(AVB0_MII_COL)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
458 
459 /* IP0SR5 */		/* 0 */			/* 1 */			/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
460 #define IP0SR5_3_0	FM(AVB1_RX_CTL)		FM(AVB1_MII_RX_DV)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
461 #define IP0SR5_7_4	FM(AVB1_RXC)		FM(AVB1_MII_RXC)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
462 #define IP0SR5_11_8	FM(AVB1_RD0)		FM(AVB1_MII_RD0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
463 #define IP0SR5_15_12	FM(AVB1_RD1)		FM(AVB1_MII_RD1)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
464 #define IP0SR5_19_16	FM(AVB1_RD2)		FM(AVB1_MII_RD2)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
465 #define IP0SR5_23_20	FM(AVB1_RD3)		FM(AVB1_MII_RD3)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
466 #define IP0SR5_27_24	FM(AVB1_TX_CTL)		FM(AVB1_MII_TX_EN)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
467 #define IP0SR5_31_28	FM(AVB1_TXC)		FM(AVB1_MII_TXC)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
468 /* IP1SR5 */		/* 0 */			/* 1 */			/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
469 #define IP1SR5_3_0	FM(AVB1_TD0)		FM(AVB1_MII_TD0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
470 #define IP1SR5_7_4	FM(AVB1_TD1)		FM(AVB1_MII_TD1)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
471 #define IP1SR5_11_8	FM(AVB1_TD2)		FM(AVB1_MII_TD2)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define IP1SR5_15_12	FM(AVB1_TD3)		FM(AVB1_MII_TD3)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
473 #define IP1SR5_19_16	FM(AVB1_TXCREFCLK)	F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
474 #define IP1SR5_23_20	FM(AVB1_MDIO)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define IP1SR5_27_24	FM(AVB1_MDC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
476 #define IP1SR5_31_28	FM(AVB1_MAGIC)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
477 /* IP2SR5 */		/* 0 */			/* 1 */			/* 2 */		/* 3 */		/* 4 */		/* 5 */		/* 6 - F */
478 #define IP2SR5_7_4	FM(AVB1_LINK)		FM(AVB1_MII_TX_ER)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
479 #define IP2SR5_11_8	FM(AVB1_AVTP_MATCH)	FM(AVB1_MII_RX_ER)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
480 #define IP2SR5_15_12	FM(AVB1_AVTP_CAPTURE)	FM(AVB1_MII_CRS)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
481 #define IP2SR5_19_16	FM(AVB1_AVTP_PPS)	FM(AVB1_MII_COL)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
482 
483 #define PINMUX_GPSR		\
484 				\
485 		GPSR1_30	\
486 		GPSR1_29	\
487 		GPSR1_28	\
488 GPSR0_27	GPSR1_27	\
489 GPSR0_26	GPSR1_26					GPSR4_26 \
490 GPSR0_25	GPSR1_25					GPSR4_25 \
491 GPSR0_24	GPSR1_24	GPSR2_24			GPSR4_24 \
492 GPSR0_23	GPSR1_23	GPSR2_23			GPSR4_23 \
493 GPSR0_22	GPSR1_22	GPSR2_22			GPSR4_22 \
494 GPSR0_21	GPSR1_21	GPSR2_21			GPSR4_21 \
495 GPSR0_20	GPSR1_20	GPSR2_20			GPSR4_20	GPSR5_20	GPSR6_20	GPSR7_20	GPSR8_20	GPSR9_20 \
496 GPSR0_19	GPSR1_19	GPSR2_19			GPSR4_19	GPSR5_19	GPSR6_19	GPSR7_19	GPSR8_19	GPSR9_19 \
497 GPSR0_18	GPSR1_18	GPSR2_18			GPSR4_18	GPSR5_18	GPSR6_18	GPSR7_18	GPSR8_18	GPSR9_18 \
498 GPSR0_17	GPSR1_17	GPSR2_17			GPSR4_17	GPSR5_17	GPSR6_17	GPSR7_17	GPSR8_17	GPSR9_17 \
499 GPSR0_16	GPSR1_16	GPSR2_16	GPSR3_16	GPSR4_16	GPSR5_16	GPSR6_16	GPSR7_16	GPSR8_16	GPSR9_16 \
500 GPSR0_15	GPSR1_15	GPSR2_15	GPSR3_15	GPSR4_15	GPSR5_15	GPSR6_15	GPSR7_15	GPSR8_15	GPSR9_15 \
501 GPSR0_14	GPSR1_14	GPSR2_14	GPSR3_14	GPSR4_14	GPSR5_14	GPSR6_14	GPSR7_14	GPSR8_14	GPSR9_14 \
502 GPSR0_13	GPSR1_13	GPSR2_13	GPSR3_13	GPSR4_13	GPSR5_13	GPSR6_13	GPSR7_13	GPSR8_13	GPSR9_13 \
503 GPSR0_12	GPSR1_12	GPSR2_12	GPSR3_12	GPSR4_12	GPSR5_12	GPSR6_12	GPSR7_12	GPSR8_12	GPSR9_12 \
504 GPSR0_11	GPSR1_11	GPSR2_11	GPSR3_11	GPSR4_11	GPSR5_11	GPSR6_11	GPSR7_11	GPSR8_11	GPSR9_11 \
505 GPSR0_10	GPSR1_10	GPSR2_10	GPSR3_10	GPSR4_10	GPSR5_10	GPSR6_10	GPSR7_10	GPSR8_10	GPSR9_10 \
506 GPSR0_9		GPSR1_9		GPSR2_9		GPSR3_9		GPSR4_9		GPSR5_9		GPSR6_9		GPSR7_9		GPSR8_9		GPSR9_9 \
507 GPSR0_8		GPSR1_8		GPSR2_8		GPSR3_8		GPSR4_8		GPSR5_8		GPSR6_8		GPSR7_8		GPSR8_8		GPSR9_8 \
508 GPSR0_7		GPSR1_7		GPSR2_7		GPSR3_7		GPSR4_7		GPSR5_7		GPSR6_7		GPSR7_7		GPSR8_7		GPSR9_7 \
509 GPSR0_6		GPSR1_6		GPSR2_6		GPSR3_6		GPSR4_6		GPSR5_6		GPSR6_6		GPSR7_6		GPSR8_6		GPSR9_6 \
510 GPSR0_5		GPSR1_5		GPSR2_5		GPSR3_5		GPSR4_5		GPSR5_5		GPSR6_5		GPSR7_5		GPSR8_5		GPSR9_5 \
511 GPSR0_4		GPSR1_4		GPSR2_4		GPSR3_4		GPSR4_4		GPSR5_4		GPSR6_4		GPSR7_4		GPSR8_4		GPSR9_4 \
512 GPSR0_3		GPSR1_3		GPSR2_3		GPSR3_3		GPSR4_3		GPSR5_3		GPSR6_3		GPSR7_3		GPSR8_3		GPSR9_3 \
513 GPSR0_2		GPSR1_2		GPSR2_2		GPSR3_2		GPSR4_2		GPSR5_2		GPSR6_2		GPSR7_2		GPSR8_2		GPSR9_2 \
514 GPSR0_1		GPSR1_1		GPSR2_1		GPSR3_1		GPSR4_1		GPSR5_1		GPSR6_1		GPSR7_1		GPSR8_1		GPSR9_1 \
515 GPSR0_0		GPSR1_0		GPSR2_0		GPSR3_0		GPSR4_0		GPSR5_0		GPSR6_0		GPSR7_0		GPSR8_0		GPSR9_0
516 
517 #define PINMUX_IPSR	\
518 \
519 FM(IP0SR1_3_0)		IP0SR1_3_0	FM(IP1SR1_3_0)		IP1SR1_3_0	FM(IP2SR1_3_0)		IP2SR1_3_0	FM(IP3SR1_3_0)		IP3SR1_3_0 \
520 FM(IP0SR1_7_4)		IP0SR1_7_4	FM(IP1SR1_7_4)		IP1SR1_7_4	FM(IP2SR1_7_4)		IP2SR1_7_4	FM(IP3SR1_7_4)		IP3SR1_7_4 \
521 FM(IP0SR1_11_8)		IP0SR1_11_8	FM(IP1SR1_11_8)		IP1SR1_11_8	FM(IP2SR1_11_8)		IP2SR1_11_8	FM(IP3SR1_11_8)		IP3SR1_11_8 \
522 FM(IP0SR1_15_12)	IP0SR1_15_12	FM(IP1SR1_15_12)	IP1SR1_15_12	FM(IP2SR1_15_12)	IP2SR1_15_12	FM(IP3SR1_15_12)	IP3SR1_15_12 \
523 FM(IP0SR1_19_16)	IP0SR1_19_16	FM(IP1SR1_19_16)	IP1SR1_19_16	FM(IP2SR1_19_16)	IP2SR1_19_16	FM(IP3SR1_19_16)	IP3SR1_19_16 \
524 FM(IP0SR1_23_20)	IP0SR1_23_20	FM(IP1SR1_23_20)	IP1SR1_23_20	FM(IP2SR1_23_20)	IP2SR1_23_20	FM(IP3SR1_23_20)	IP3SR1_23_20 \
525 FM(IP0SR1_27_24)	IP0SR1_27_24	FM(IP1SR1_27_24)	IP1SR1_27_24	FM(IP2SR1_27_24)	IP2SR1_27_24	FM(IP3SR1_27_24)	IP3SR1_27_24 \
526 FM(IP0SR1_31_28)	IP0SR1_31_28	FM(IP1SR1_31_28)	IP1SR1_31_28	FM(IP2SR1_31_28)	IP2SR1_31_28 \
527 \
528 FM(IP0SR2_3_0)		IP0SR2_3_0	FM(IP1SR2_3_0)		IP1SR2_3_0	FM(IP2SR2_3_0)		IP2SR2_3_0 \
529 FM(IP0SR2_7_4)		IP0SR2_7_4	FM(IP1SR2_7_4)		IP1SR2_7_4	FM(IP2SR2_7_4)		IP2SR2_7_4 \
530 FM(IP0SR2_11_8)		IP0SR2_11_8	FM(IP1SR2_11_8)		IP1SR2_11_8	FM(IP2SR2_11_8)		IP2SR2_11_8 \
531 FM(IP0SR2_15_12)	IP0SR2_15_12	FM(IP1SR2_15_12)	IP1SR2_15_12	FM(IP2SR2_15_12)	IP2SR2_15_12 \
532 FM(IP0SR2_19_16)	IP0SR2_19_16	FM(IP1SR2_19_16)	IP1SR2_19_16	FM(IP2SR2_19_16)	IP2SR2_19_16 \
533 FM(IP0SR2_23_20)	IP0SR2_23_20	FM(IP1SR2_23_20)	IP1SR2_23_20	FM(IP2SR2_23_20)	IP2SR2_23_20 \
534 FM(IP0SR2_27_24)	IP0SR2_27_24	FM(IP1SR2_27_24)	IP1SR2_27_24	FM(IP2SR2_27_24)	IP2SR2_27_24 \
535 FM(IP0SR2_31_28)	IP0SR2_31_28	FM(IP1SR2_31_28)	IP1SR2_31_28	FM(IP2SR2_31_28)	IP2SR2_31_28 \
536 \
537 					FM(IP1SR3_3_0)		IP1SR3_3_0	\
538 FM(IP0SR3_7_4)		IP0SR3_7_4	FM(IP1SR3_7_4)		IP1SR3_7_4	\
539 FM(IP0SR3_11_8)		IP0SR3_11_8	FM(IP1SR3_11_8)		IP1SR3_11_8	\
540 					FM(IP1SR3_15_12)	IP1SR3_15_12	\
541 					FM(IP1SR3_19_16)	IP1SR3_19_16	\
542 FM(IP0SR3_23_20)	IP0SR3_23_20	FM(IP1SR3_23_20)	IP1SR3_23_20	\
543 FM(IP0SR3_27_24)	IP0SR3_27_24	\
544 FM(IP0SR3_31_28)	IP0SR3_31_28	\
545 \
546 FM(IP0SR4_3_0)		IP0SR4_3_0	FM(IP1SR4_3_0)		IP1SR4_3_0	\
547 FM(IP0SR4_7_4)		IP0SR4_7_4	FM(IP1SR4_7_4)		IP1SR4_7_4	FM(IP2SR4_7_4)		IP2SR4_7_4 \
548 FM(IP0SR4_11_8)		IP0SR4_11_8	FM(IP1SR4_11_8)		IP1SR4_11_8	FM(IP2SR4_11_8)		IP2SR4_11_8 \
549 FM(IP0SR4_15_12)	IP0SR4_15_12	FM(IP1SR4_15_12)	IP1SR4_15_12	FM(IP2SR4_15_12)	IP2SR4_15_12 \
550 FM(IP0SR4_19_16)	IP0SR4_19_16	FM(IP1SR4_19_16)	IP1SR4_19_16	FM(IP2SR4_19_16)	IP2SR4_19_16 \
551 FM(IP0SR4_23_20)	IP0SR4_23_20	FM(IP1SR4_23_20)	IP1SR4_23_20	\
552 FM(IP0SR4_27_24)	IP0SR4_27_24	FM(IP1SR4_27_24)	IP1SR4_27_24	\
553 FM(IP0SR4_31_28)	IP0SR4_31_28	FM(IP1SR4_31_28)	IP1SR4_31_28	\
554 \
555 FM(IP0SR5_3_0)		IP0SR5_3_0	FM(IP1SR5_3_0)		IP1SR5_3_0	\
556 FM(IP0SR5_7_4)		IP0SR5_7_4	FM(IP1SR5_7_4)		IP1SR5_7_4	FM(IP2SR5_7_4)		IP2SR5_7_4 \
557 FM(IP0SR5_11_8)		IP0SR5_11_8	FM(IP1SR5_11_8)		IP1SR5_11_8	FM(IP2SR5_11_8)		IP2SR5_11_8 \
558 FM(IP0SR5_15_12)	IP0SR5_15_12	FM(IP1SR5_15_12)	IP1SR5_15_12	FM(IP2SR5_15_12)	IP2SR5_15_12 \
559 FM(IP0SR5_19_16)	IP0SR5_19_16	FM(IP1SR5_19_16)	IP1SR5_19_16	FM(IP2SR5_19_16)	IP2SR5_19_16 \
560 FM(IP0SR5_23_20)	IP0SR5_23_20	FM(IP1SR5_23_20)	IP1SR5_23_20	\
561 FM(IP0SR5_27_24)	IP0SR5_27_24	FM(IP1SR5_27_24)	IP1SR5_27_24	\
562 FM(IP0SR5_31_28)	IP0SR5_31_28	FM(IP1SR5_31_28)	IP1SR5_31_28
563 
564 /* MOD_SEL2 */			/* 0 */		/* 1 */		/* 2 */		/* 3 */
565 #define MOD_SEL2_15_14		FM(SEL_I2C6_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C6_3)
566 #define MOD_SEL2_13_12		FM(SEL_I2C5_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C5_3)
567 #define MOD_SEL2_11_10		FM(SEL_I2C4_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C4_3)
568 #define MOD_SEL2_9_8		FM(SEL_I2C3_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C3_3)
569 #define MOD_SEL2_7_6		FM(SEL_I2C2_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C2_3)
570 #define MOD_SEL2_5_4		FM(SEL_I2C1_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C1_3)
571 #define MOD_SEL2_3_2		FM(SEL_I2C0_0)	F_(0, 0)	F_(0, 0)	FM(SEL_I2C0_3)
572 
573 #define PINMUX_MOD_SELS \
574 \
575 MOD_SEL2_15_14 \
576 MOD_SEL2_13_12 \
577 MOD_SEL2_11_10 \
578 MOD_SEL2_9_8 \
579 MOD_SEL2_7_6 \
580 MOD_SEL2_5_4 \
581 MOD_SEL2_3_2
582 
583 #define PINMUX_PHYS \
584 	FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \
585 	FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) FM(SCL6) FM(SDA6)
586 
587 enum {
588 	PINMUX_RESERVED = 0,
589 
590 	PINMUX_DATA_BEGIN,
591 	GP_ALL(DATA),
592 	PINMUX_DATA_END,
593 
594 #define F_(x, y)
595 #define FM(x)   FN_##x,
596 	PINMUX_FUNCTION_BEGIN,
597 	GP_ALL(FN),
598 	PINMUX_GPSR
599 	PINMUX_IPSR
600 	PINMUX_MOD_SELS
601 	PINMUX_FUNCTION_END,
602 #undef F_
603 #undef FM
604 
605 #define F_(x, y)
606 #define FM(x)	x##_MARK,
607 	PINMUX_MARK_BEGIN,
608 	PINMUX_GPSR
609 	PINMUX_IPSR
610 	PINMUX_MOD_SELS
611 	PINMUX_PHYS
612 	PINMUX_MARK_END,
613 #undef F_
614 #undef FM
615 };
616 
617 static const u16 pinmux_data[] = {
618 /* Using GP_2_[2-15] requires disabling I2C in MOD_SEL2 */
619 #define GP_2_2_FN	GP_2_2_FN,	FN_SEL_I2C0_0
620 #define GP_2_3_FN	GP_2_3_FN,	FN_SEL_I2C0_0
621 #define GP_2_4_FN	GP_2_4_FN,	FN_SEL_I2C1_0
622 #define GP_2_5_FN	GP_2_5_FN,	FN_SEL_I2C1_0
623 #define GP_2_6_FN	GP_2_6_FN,	FN_SEL_I2C2_0
624 #define GP_2_7_FN	GP_2_7_FN,	FN_SEL_I2C2_0
625 #define GP_2_8_FN	GP_2_8_FN,	FN_SEL_I2C3_0
626 #define GP_2_9_FN	GP_2_9_FN,	FN_SEL_I2C3_0
627 #define GP_2_10_FN	GP_2_10_FN,	FN_SEL_I2C4_0
628 #define GP_2_11_FN	GP_2_11_FN,	FN_SEL_I2C4_0
629 #define GP_2_12_FN	GP_2_12_FN,	FN_SEL_I2C5_0
630 #define GP_2_13_FN	GP_2_13_FN,	FN_SEL_I2C5_0
631 #define GP_2_14_FN	GP_2_14_FN,	FN_SEL_I2C6_0
632 #define GP_2_15_FN	GP_2_15_FN,	FN_SEL_I2C6_0
633 	PINMUX_DATA_GP_ALL(),
634 #undef GP_2_2_FN
635 #undef GP_2_3_FN
636 #undef GP_2_4_FN
637 #undef GP_2_5_FN
638 #undef GP_2_6_FN
639 #undef GP_2_7_FN
640 #undef GP_2_8_FN
641 #undef GP_2_9_FN
642 #undef GP_2_10_FN
643 #undef GP_2_11_FN
644 #undef GP_2_12_FN
645 #undef GP_2_13_FN
646 #undef GP_2_14_FN
647 #undef GP_2_15_FN
648 
649 	PINMUX_SINGLE(MMC_D7),
650 	PINMUX_SINGLE(MMC_D6),
651 	PINMUX_SINGLE(MMC_D5),
652 	PINMUX_SINGLE(MMC_D4),
653 	PINMUX_SINGLE(MMC_SD_CLK),
654 	PINMUX_SINGLE(MMC_SD_D3),
655 	PINMUX_SINGLE(MMC_SD_D2),
656 	PINMUX_SINGLE(MMC_SD_D1),
657 	PINMUX_SINGLE(MMC_SD_D0),
658 	PINMUX_SINGLE(MMC_SD_CMD),
659 	PINMUX_SINGLE(MMC_DS),
660 
661 	PINMUX_SINGLE(SD_CD),
662 	PINMUX_SINGLE(SD_WP),
663 
664 	PINMUX_SINGLE(RPC_INT_N),
665 	PINMUX_SINGLE(RPC_WP_N),
666 	PINMUX_SINGLE(RPC_RESET_N),
667 
668 	PINMUX_SINGLE(QSPI1_SSL),
669 	PINMUX_SINGLE(QSPI1_IO3),
670 	PINMUX_SINGLE(QSPI1_IO2),
671 	PINMUX_SINGLE(QSPI1_MISO_IO1),
672 	PINMUX_SINGLE(QSPI1_MOSI_IO0),
673 	PINMUX_SINGLE(QSPI1_SPCLK),
674 	PINMUX_SINGLE(QSPI0_SSL),
675 	PINMUX_SINGLE(QSPI0_IO3),
676 	PINMUX_SINGLE(QSPI0_IO2),
677 	PINMUX_SINGLE(QSPI0_MISO_IO1),
678 	PINMUX_SINGLE(QSPI0_MOSI_IO0),
679 	PINMUX_SINGLE(QSPI0_SPCLK),
680 
681 	PINMUX_SINGLE(TCLK2_A),
682 
683 	PINMUX_SINGLE(CANFD7_RX),
684 	PINMUX_SINGLE(CANFD7_TX),
685 	PINMUX_SINGLE(CANFD6_RX),
686 	PINMUX_SINGLE(CANFD1_RX),
687 	PINMUX_SINGLE(CANFD1_TX),
688 	PINMUX_SINGLE(CAN_CLK),
689 
690 	PINMUX_SINGLE(AVS1),
691 	PINMUX_SINGLE(AVS0),
692 
693 	PINMUX_SINGLE(PCIE3_CLKREQ_N),
694 	PINMUX_SINGLE(PCIE2_CLKREQ_N),
695 	PINMUX_SINGLE(PCIE1_CLKREQ_N),
696 	PINMUX_SINGLE(PCIE0_CLKREQ_N),
697 
698 	PINMUX_SINGLE(AVB0_PHY_INT),
699 	PINMUX_SINGLE(AVB0_MAGIC),
700 	PINMUX_SINGLE(AVB0_MDC),
701 	PINMUX_SINGLE(AVB0_MDIO),
702 	PINMUX_SINGLE(AVB0_TXCREFCLK),
703 
704 	PINMUX_SINGLE(AVB1_PHY_INT),
705 	PINMUX_SINGLE(AVB1_MAGIC),
706 	PINMUX_SINGLE(AVB1_MDC),
707 	PINMUX_SINGLE(AVB1_MDIO),
708 	PINMUX_SINGLE(AVB1_TXCREFCLK),
709 
710 	PINMUX_SINGLE(AVB2_AVTP_PPS),
711 	PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
712 	PINMUX_SINGLE(AVB2_AVTP_MATCH),
713 	PINMUX_SINGLE(AVB2_LINK),
714 	PINMUX_SINGLE(AVB2_PHY_INT),
715 	PINMUX_SINGLE(AVB2_MAGIC),
716 	PINMUX_SINGLE(AVB2_MDC),
717 	PINMUX_SINGLE(AVB2_MDIO),
718 	PINMUX_SINGLE(AVB2_TXCREFCLK),
719 	PINMUX_SINGLE(AVB2_TD3),
720 	PINMUX_SINGLE(AVB2_TD2),
721 	PINMUX_SINGLE(AVB2_TD1),
722 	PINMUX_SINGLE(AVB2_TD0),
723 	PINMUX_SINGLE(AVB2_TXC),
724 	PINMUX_SINGLE(AVB2_TX_CTL),
725 	PINMUX_SINGLE(AVB2_RD3),
726 	PINMUX_SINGLE(AVB2_RD2),
727 	PINMUX_SINGLE(AVB2_RD1),
728 	PINMUX_SINGLE(AVB2_RD0),
729 	PINMUX_SINGLE(AVB2_RXC),
730 	PINMUX_SINGLE(AVB2_RX_CTL),
731 
732 	PINMUX_SINGLE(AVB3_AVTP_PPS),
733 	PINMUX_SINGLE(AVB3_AVTP_CAPTURE),
734 	PINMUX_SINGLE(AVB3_AVTP_MATCH),
735 	PINMUX_SINGLE(AVB3_LINK),
736 	PINMUX_SINGLE(AVB3_PHY_INT),
737 	PINMUX_SINGLE(AVB3_MAGIC),
738 	PINMUX_SINGLE(AVB3_MDC),
739 	PINMUX_SINGLE(AVB3_MDIO),
740 	PINMUX_SINGLE(AVB3_TXCREFCLK),
741 	PINMUX_SINGLE(AVB3_TD3),
742 	PINMUX_SINGLE(AVB3_TD2),
743 	PINMUX_SINGLE(AVB3_TD1),
744 	PINMUX_SINGLE(AVB3_TD0),
745 	PINMUX_SINGLE(AVB3_TXC),
746 	PINMUX_SINGLE(AVB3_TX_CTL),
747 	PINMUX_SINGLE(AVB3_RD3),
748 	PINMUX_SINGLE(AVB3_RD2),
749 	PINMUX_SINGLE(AVB3_RD1),
750 	PINMUX_SINGLE(AVB3_RD0),
751 	PINMUX_SINGLE(AVB3_RXC),
752 	PINMUX_SINGLE(AVB3_RX_CTL),
753 
754 	PINMUX_SINGLE(AVB4_AVTP_PPS),
755 	PINMUX_SINGLE(AVB4_AVTP_CAPTURE),
756 	PINMUX_SINGLE(AVB4_AVTP_MATCH),
757 	PINMUX_SINGLE(AVB4_LINK),
758 	PINMUX_SINGLE(AVB4_PHY_INT),
759 	PINMUX_SINGLE(AVB4_MAGIC),
760 	PINMUX_SINGLE(AVB4_MDC),
761 	PINMUX_SINGLE(AVB4_MDIO),
762 	PINMUX_SINGLE(AVB4_TXCREFCLK),
763 	PINMUX_SINGLE(AVB4_TD3),
764 	PINMUX_SINGLE(AVB4_TD2),
765 	PINMUX_SINGLE(AVB4_TD1),
766 	PINMUX_SINGLE(AVB4_TD0),
767 	PINMUX_SINGLE(AVB4_TXC),
768 	PINMUX_SINGLE(AVB4_TX_CTL),
769 	PINMUX_SINGLE(AVB4_RD3),
770 	PINMUX_SINGLE(AVB4_RD2),
771 	PINMUX_SINGLE(AVB4_RD1),
772 	PINMUX_SINGLE(AVB4_RD0),
773 	PINMUX_SINGLE(AVB4_RXC),
774 	PINMUX_SINGLE(AVB4_RX_CTL),
775 
776 	PINMUX_SINGLE(AVB5_AVTP_PPS),
777 	PINMUX_SINGLE(AVB5_AVTP_CAPTURE),
778 	PINMUX_SINGLE(AVB5_AVTP_MATCH),
779 	PINMUX_SINGLE(AVB5_LINK),
780 	PINMUX_SINGLE(AVB5_PHY_INT),
781 	PINMUX_SINGLE(AVB5_MAGIC),
782 	PINMUX_SINGLE(AVB5_MDC),
783 	PINMUX_SINGLE(AVB5_MDIO),
784 	PINMUX_SINGLE(AVB5_TXCREFCLK),
785 	PINMUX_SINGLE(AVB5_TD3),
786 	PINMUX_SINGLE(AVB5_TD2),
787 	PINMUX_SINGLE(AVB5_TD1),
788 	PINMUX_SINGLE(AVB5_TD0),
789 	PINMUX_SINGLE(AVB5_TXC),
790 	PINMUX_SINGLE(AVB5_TX_CTL),
791 	PINMUX_SINGLE(AVB5_RD3),
792 	PINMUX_SINGLE(AVB5_RD2),
793 	PINMUX_SINGLE(AVB5_RD1),
794 	PINMUX_SINGLE(AVB5_RD0),
795 	PINMUX_SINGLE(AVB5_RXC),
796 	PINMUX_SINGLE(AVB5_RX_CTL),
797 
798 	/* IP0SR1 */
799 	PINMUX_IPSR_GPSR(IP0SR1_3_0,	SCIF_CLK),
800 	PINMUX_IPSR_GPSR(IP0SR1_3_0,	A0),
801 
802 	PINMUX_IPSR_GPSR(IP0SR1_7_4,	HRX0),
803 	PINMUX_IPSR_GPSR(IP0SR1_7_4,	RX0),
804 	PINMUX_IPSR_GPSR(IP0SR1_7_4,	A1),
805 
806 	PINMUX_IPSR_GPSR(IP0SR1_11_8,	HSCK0),
807 	PINMUX_IPSR_GPSR(IP0SR1_11_8,	SCK0),
808 	PINMUX_IPSR_GPSR(IP0SR1_11_8,	A2),
809 
810 	PINMUX_IPSR_GPSR(IP0SR1_15_12,	HRTS0_N),
811 	PINMUX_IPSR_GPSR(IP0SR1_15_12,	RTS0_N),
812 	PINMUX_IPSR_GPSR(IP0SR1_15_12,	A3),
813 
814 	PINMUX_IPSR_GPSR(IP0SR1_19_16,	HCTS0_N),
815 	PINMUX_IPSR_GPSR(IP0SR1_19_16,	CTS0_N),
816 	PINMUX_IPSR_GPSR(IP0SR1_19_16,	A4),
817 
818 	PINMUX_IPSR_GPSR(IP0SR1_23_20,	HTX0),
819 	PINMUX_IPSR_GPSR(IP0SR1_23_20,	TX0),
820 	PINMUX_IPSR_GPSR(IP0SR1_23_20,	A5),
821 
822 	PINMUX_IPSR_GPSR(IP0SR1_27_24,	MSIOF0_RXD),
823 	PINMUX_IPSR_GPSR(IP0SR1_27_24,	DU_DR2),
824 	PINMUX_IPSR_GPSR(IP0SR1_27_24,	A6),
825 
826 	PINMUX_IPSR_GPSR(IP0SR1_31_28,	MSIOF0_TXD),
827 	PINMUX_IPSR_GPSR(IP0SR1_31_28,	DU_DR3),
828 	PINMUX_IPSR_GPSR(IP0SR1_31_28,	A7),
829 
830 	/* IP1SR1 */
831 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	MSIOF0_SCK),
832 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	DU_DR4),
833 	PINMUX_IPSR_GPSR(IP1SR1_3_0,	A8),
834 
835 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	MSIOF0_SYNC),
836 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	DU_DR5),
837 	PINMUX_IPSR_GPSR(IP1SR1_7_4,	A9),
838 
839 	PINMUX_IPSR_GPSR(IP1SR1_11_8,	MSIOF0_SS1),
840 	PINMUX_IPSR_GPSR(IP1SR1_11_8,	DU_DR6),
841 	PINMUX_IPSR_GPSR(IP1SR1_11_8,	A10),
842 
843 	PINMUX_IPSR_GPSR(IP1SR1_15_12,	MSIOF0_SS2),
844 	PINMUX_IPSR_GPSR(IP1SR1_15_12,	DU_DR7),
845 	PINMUX_IPSR_GPSR(IP1SR1_15_12,	A11),
846 
847 	PINMUX_IPSR_GPSR(IP1SR1_19_16,	MSIOF1_RXD),
848 	PINMUX_IPSR_GPSR(IP1SR1_19_16,	DU_DG2),
849 	PINMUX_IPSR_GPSR(IP1SR1_19_16,	A12),
850 
851 	PINMUX_IPSR_GPSR(IP1SR1_23_20,	MSIOF1_TXD),
852 	PINMUX_IPSR_GPSR(IP1SR1_23_20,	HRX3),
853 	PINMUX_IPSR_GPSR(IP1SR1_23_20,	SCK3),
854 	PINMUX_IPSR_GPSR(IP1SR1_23_20,	DU_DG3),
855 	PINMUX_IPSR_GPSR(IP1SR1_23_20,	A13),
856 
857 	PINMUX_IPSR_GPSR(IP1SR1_27_24,	MSIOF1_SCK),
858 	PINMUX_IPSR_GPSR(IP1SR1_27_24,	HSCK3),
859 	PINMUX_IPSR_GPSR(IP1SR1_27_24,	CTS3_N),
860 	PINMUX_IPSR_GPSR(IP1SR1_27_24,	DU_DG4),
861 	PINMUX_IPSR_GPSR(IP1SR1_27_24,	A14),
862 
863 	PINMUX_IPSR_GPSR(IP1SR1_31_28,	MSIOF1_SYNC),
864 	PINMUX_IPSR_GPSR(IP1SR1_31_28,	HRTS3_N),
865 	PINMUX_IPSR_GPSR(IP1SR1_31_28,	RTS3_N),
866 	PINMUX_IPSR_GPSR(IP1SR1_31_28,	DU_DG5),
867 	PINMUX_IPSR_GPSR(IP1SR1_31_28,	A15),
868 
869 	/* IP2SR1 */
870 	PINMUX_IPSR_GPSR(IP2SR1_3_0,	MSIOF1_SS1),
871 	PINMUX_IPSR_GPSR(IP2SR1_3_0,	HCTS3_N),
872 	PINMUX_IPSR_GPSR(IP2SR1_3_0,	RX3),
873 	PINMUX_IPSR_GPSR(IP2SR1_3_0,	DU_DG6),
874 	PINMUX_IPSR_GPSR(IP2SR1_3_0,	A16),
875 
876 	PINMUX_IPSR_GPSR(IP2SR1_7_4,	MSIOF1_SS2),
877 	PINMUX_IPSR_GPSR(IP2SR1_7_4,	HTX3),
878 	PINMUX_IPSR_GPSR(IP2SR1_7_4,	TX3),
879 	PINMUX_IPSR_GPSR(IP2SR1_7_4,	DU_DG7),
880 	PINMUX_IPSR_GPSR(IP2SR1_7_4,	A17),
881 
882 	PINMUX_IPSR_GPSR(IP2SR1_11_8,	MSIOF2_RXD),
883 	PINMUX_IPSR_GPSR(IP2SR1_11_8,	HSCK1),
884 	PINMUX_IPSR_GPSR(IP2SR1_11_8,	SCK1),
885 	PINMUX_IPSR_GPSR(IP2SR1_11_8,	DU_DB2),
886 	PINMUX_IPSR_GPSR(IP2SR1_11_8,	A18),
887 
888 	PINMUX_IPSR_GPSR(IP2SR1_15_12,	MSIOF2_TXD),
889 	PINMUX_IPSR_GPSR(IP2SR1_15_12,	HCTS1_N),
890 	PINMUX_IPSR_GPSR(IP2SR1_15_12,	CTS1_N),
891 	PINMUX_IPSR_GPSR(IP2SR1_15_12,	DU_DB3),
892 	PINMUX_IPSR_GPSR(IP2SR1_15_12,	A19),
893 
894 	PINMUX_IPSR_GPSR(IP2SR1_19_16,	MSIOF2_SCK),
895 	PINMUX_IPSR_GPSR(IP2SR1_19_16,	HRTS1_N),
896 	PINMUX_IPSR_GPSR(IP2SR1_19_16,	RTS1_N),
897 	PINMUX_IPSR_GPSR(IP2SR1_19_16,	DU_DB4),
898 	PINMUX_IPSR_GPSR(IP2SR1_19_16,	A20),
899 
900 	PINMUX_IPSR_GPSR(IP2SR1_23_20,	MSIOF2_SYNC),
901 	PINMUX_IPSR_GPSR(IP2SR1_23_20,	HRX1),
902 	PINMUX_IPSR_GPSR(IP2SR1_23_20,	RX1_A),
903 	PINMUX_IPSR_GPSR(IP2SR1_23_20,	DU_DB5),
904 	PINMUX_IPSR_GPSR(IP2SR1_23_20,	A21),
905 
906 	PINMUX_IPSR_GPSR(IP2SR1_27_24,	MSIOF2_SS1),
907 	PINMUX_IPSR_GPSR(IP2SR1_27_24,	HTX1),
908 	PINMUX_IPSR_GPSR(IP2SR1_27_24,	TX1_A),
909 	PINMUX_IPSR_GPSR(IP2SR1_27_24,	DU_DB6),
910 	PINMUX_IPSR_GPSR(IP2SR1_27_24,	A22),
911 
912 	PINMUX_IPSR_GPSR(IP2SR1_31_28,	MSIOF2_SS2),
913 	PINMUX_IPSR_GPSR(IP2SR1_31_28,	TCLK1_B),
914 	PINMUX_IPSR_GPSR(IP2SR1_31_28,	DU_DB7),
915 	PINMUX_IPSR_GPSR(IP2SR1_31_28,	A23),
916 
917 	/* IP3SR1 */
918 	PINMUX_IPSR_GPSR(IP3SR1_3_0,	IRQ0),
919 	PINMUX_IPSR_GPSR(IP3SR1_3_0,	DU_DOTCLKOUT),
920 	PINMUX_IPSR_GPSR(IP3SR1_3_0,	A24),
921 
922 	PINMUX_IPSR_GPSR(IP3SR1_7_4,	IRQ1),
923 	PINMUX_IPSR_GPSR(IP3SR1_7_4,	DU_HSYNC),
924 	PINMUX_IPSR_GPSR(IP3SR1_7_4,	A25),
925 
926 	PINMUX_IPSR_GPSR(IP3SR1_11_8,	IRQ2),
927 	PINMUX_IPSR_GPSR(IP3SR1_11_8,	DU_VSYNC),
928 	PINMUX_IPSR_GPSR(IP3SR1_11_8,	CS1_N_A26),
929 
930 	PINMUX_IPSR_GPSR(IP3SR1_15_12,	IRQ3),
931 	PINMUX_IPSR_GPSR(IP3SR1_15_12,	DU_ODDF_DISP_CDE),
932 	PINMUX_IPSR_GPSR(IP3SR1_15_12,	CS0_N),
933 
934 	PINMUX_IPSR_GPSR(IP3SR1_19_16,	GP1_28),
935 	PINMUX_IPSR_GPSR(IP3SR1_19_16,	D0),
936 
937 	PINMUX_IPSR_GPSR(IP3SR1_23_20,	GP1_29),
938 	PINMUX_IPSR_GPSR(IP3SR1_23_20,	D1),
939 
940 	PINMUX_IPSR_GPSR(IP3SR1_27_24,	GP1_30),
941 	PINMUX_IPSR_GPSR(IP3SR1_27_24,	D2),
942 
943 	/* IP0SR2 */
944 	PINMUX_IPSR_GPSR(IP0SR2_3_0,	IPC_CLKIN),
945 	PINMUX_IPSR_GPSR(IP0SR2_3_0,	IPC_CLKEN_IN),
946 	PINMUX_IPSR_GPSR(IP0SR2_3_0,	DU_DOTCLKIN),
947 
948 	PINMUX_IPSR_GPSR(IP0SR2_7_4,	IPC_CLKOUT),
949 	PINMUX_IPSR_GPSR(IP0SR2_7_4,	IPC_CLKEN_OUT),
950 
951 	/* GP2_02 = SCL0 */
952 	PINMUX_IPSR_MSEL(IP0SR2_11_8,	GP2_02,	SEL_I2C0_0),
953 	PINMUX_IPSR_MSEL(IP0SR2_11_8,	D3,	SEL_I2C0_0),
954 	PINMUX_IPSR_PHYS(IP0SR2_11_8,	SCL0,	SEL_I2C0_3),
955 
956 	/* GP2_03 = SDA0 */
957 	PINMUX_IPSR_MSEL(IP0SR2_15_12,	GP2_03,	SEL_I2C0_0),
958 	PINMUX_IPSR_MSEL(IP0SR2_15_12,	D4,	SEL_I2C0_0),
959 	PINMUX_IPSR_PHYS(IP0SR2_15_12,	SDA0,	SEL_I2C0_3),
960 
961 	/* GP2_04 = SCL1 */
962 	PINMUX_IPSR_MSEL(IP0SR2_19_16,	GP2_04,		SEL_I2C1_0),
963 	PINMUX_IPSR_MSEL(IP0SR2_19_16,	MSIOF4_RXD,	SEL_I2C1_0),
964 	PINMUX_IPSR_MSEL(IP0SR2_19_16,	D5,		SEL_I2C1_0),
965 	PINMUX_IPSR_PHYS(IP0SR2_19_16,	SCL1,		SEL_I2C1_3),
966 
967 	/* GP2_05 = SDA1 */
968 	PINMUX_IPSR_MSEL(IP0SR2_23_20,	GP2_05,		SEL_I2C1_0),
969 	PINMUX_IPSR_MSEL(IP0SR2_23_20,	HSCK2,		SEL_I2C1_0),
970 	PINMUX_IPSR_MSEL(IP0SR2_23_20,	MSIOF4_TXD,	SEL_I2C1_0),
971 	PINMUX_IPSR_MSEL(IP0SR2_23_20,	SCK4,		SEL_I2C1_0),
972 	PINMUX_IPSR_MSEL(IP0SR2_23_20,	D6,		SEL_I2C1_0),
973 	PINMUX_IPSR_PHYS(IP0SR2_23_20,	SDA1,		SEL_I2C1_3),
974 
975 	/* GP2_06 = SCL2 */
976 	PINMUX_IPSR_MSEL(IP0SR2_27_24,	GP2_06,		SEL_I2C2_0),
977 	PINMUX_IPSR_MSEL(IP0SR2_27_24,	HCTS2_N,	SEL_I2C2_0),
978 	PINMUX_IPSR_MSEL(IP0SR2_27_24,	MSIOF4_SCK,	SEL_I2C2_0),
979 	PINMUX_IPSR_MSEL(IP0SR2_27_24,	CTS4_N,		SEL_I2C2_0),
980 	PINMUX_IPSR_MSEL(IP0SR2_27_24,	D7,		SEL_I2C2_0),
981 	PINMUX_IPSR_PHYS(IP0SR2_27_24,	SCL2,		SEL_I2C2_3),
982 
983 	/* GP2_07 = SDA2 */
984 	PINMUX_IPSR_MSEL(IP0SR2_31_28,	GP2_07,		SEL_I2C2_0),
985 	PINMUX_IPSR_MSEL(IP0SR2_31_28,	HRTS2_N,	SEL_I2C2_0),
986 	PINMUX_IPSR_MSEL(IP0SR2_31_28,	MSIOF4_SYNC,	SEL_I2C2_0),
987 	PINMUX_IPSR_MSEL(IP0SR2_31_28,	RTS4_N,		SEL_I2C2_0),
988 	PINMUX_IPSR_MSEL(IP0SR2_31_28,	D8,		SEL_I2C2_0),
989 	PINMUX_IPSR_PHYS(IP0SR2_31_28,	SDA2,		SEL_I2C2_3),
990 
991 	/* GP2_08 = SCL3 */
992 	PINMUX_IPSR_MSEL(IP1SR2_3_0,	GP2_08,		SEL_I2C3_0),
993 	PINMUX_IPSR_MSEL(IP1SR2_3_0,	HRX2,		SEL_I2C3_0),
994 	PINMUX_IPSR_MSEL(IP1SR2_3_0,	MSIOF4_SS1,	SEL_I2C3_0),
995 	PINMUX_IPSR_MSEL(IP1SR2_3_0,	RX4,		SEL_I2C3_0),
996 	PINMUX_IPSR_MSEL(IP1SR2_3_0,	D9,		SEL_I2C3_0),
997 	PINMUX_IPSR_PHYS(IP1SR2_3_0,	SCL3,		SEL_I2C3_3),
998 
999 	/* GP2_09 = SDA3 */
1000 	PINMUX_IPSR_MSEL(IP1SR2_7_4,	GP2_09,		SEL_I2C3_0),
1001 	PINMUX_IPSR_MSEL(IP1SR2_7_4,	HTX2,		SEL_I2C3_0),
1002 	PINMUX_IPSR_MSEL(IP1SR2_7_4,	MSIOF4_SS2,	SEL_I2C3_0),
1003 	PINMUX_IPSR_MSEL(IP1SR2_7_4,	TX4,		SEL_I2C3_0),
1004 	PINMUX_IPSR_MSEL(IP1SR2_7_4,	D10,		SEL_I2C3_0),
1005 	PINMUX_IPSR_PHYS(IP1SR2_7_4,	SDA3,		SEL_I2C3_3),
1006 
1007 	/* GP2_10 = SCL4 */
1008 	PINMUX_IPSR_MSEL(IP1SR2_11_8,	GP2_10,		SEL_I2C4_0),
1009 	PINMUX_IPSR_MSEL(IP1SR2_11_8,	TCLK2_B,	SEL_I2C4_0),
1010 	PINMUX_IPSR_MSEL(IP1SR2_11_8,	MSIOF5_RXD,	SEL_I2C4_0),
1011 	PINMUX_IPSR_MSEL(IP1SR2_11_8,	D11,		SEL_I2C4_0),
1012 	PINMUX_IPSR_PHYS(IP1SR2_11_8,	SCL4,		SEL_I2C4_3),
1013 
1014 	/* GP2_11 = SDA4 */
1015 	PINMUX_IPSR_MSEL(IP1SR2_15_12,	GP2_11,		SEL_I2C4_0),
1016 	PINMUX_IPSR_MSEL(IP1SR2_15_12,	TCLK3,		SEL_I2C4_0),
1017 	PINMUX_IPSR_MSEL(IP1SR2_15_12,	MSIOF5_TXD,	SEL_I2C4_0),
1018 	PINMUX_IPSR_MSEL(IP1SR2_15_12,	D12,		SEL_I2C4_0),
1019 	PINMUX_IPSR_PHYS(IP1SR2_15_12,	SDA4,		SEL_I2C4_3),
1020 
1021 	/* GP2_12 = SCL5 */
1022 	PINMUX_IPSR_MSEL(IP1SR2_19_16,	GP2_12,		SEL_I2C5_0),
1023 	PINMUX_IPSR_MSEL(IP1SR2_19_16,	TCLK4,		SEL_I2C5_0),
1024 	PINMUX_IPSR_MSEL(IP1SR2_19_16,	MSIOF5_SCK,	SEL_I2C5_0),
1025 	PINMUX_IPSR_MSEL(IP1SR2_19_16,	D13,		SEL_I2C5_0),
1026 	PINMUX_IPSR_PHYS(IP1SR2_19_16,	SCL5,		SEL_I2C5_3),
1027 
1028 	/* GP2_13 = SDA5 */
1029 	PINMUX_IPSR_MSEL(IP1SR2_23_20,	GP2_13,		SEL_I2C5_0),
1030 	PINMUX_IPSR_MSEL(IP1SR2_23_20,	MSIOF5_SYNC,	SEL_I2C5_0),
1031 	PINMUX_IPSR_MSEL(IP1SR2_23_20,	D14,		SEL_I2C5_0),
1032 	PINMUX_IPSR_PHYS(IP1SR2_23_20,	SDA5,		SEL_I2C5_3),
1033 
1034 	/* GP2_14 = SCL6 */
1035 	PINMUX_IPSR_MSEL(IP1SR2_27_24,	GP2_14,		SEL_I2C6_0),
1036 	PINMUX_IPSR_MSEL(IP1SR2_27_24,	IRQ4,		SEL_I2C6_0),
1037 	PINMUX_IPSR_MSEL(IP1SR2_27_24,	MSIOF5_SS1,	SEL_I2C6_0),
1038 	PINMUX_IPSR_MSEL(IP1SR2_27_24,	D15,		SEL_I2C6_0),
1039 	PINMUX_IPSR_PHYS(IP1SR2_27_24,	SCL6,		SEL_I2C6_3),
1040 
1041 	/* GP2_15 = SDA6 */
1042 	PINMUX_IPSR_MSEL(IP1SR2_31_28,	GP2_15,		SEL_I2C6_0),
1043 	PINMUX_IPSR_MSEL(IP1SR2_31_28,	IRQ5,		SEL_I2C6_0),
1044 	PINMUX_IPSR_MSEL(IP1SR2_31_28,	MSIOF5_SS2,	SEL_I2C6_0),
1045 	PINMUX_IPSR_MSEL(IP1SR2_31_28,	CPG_CPCKOUT,	SEL_I2C6_0),
1046 	PINMUX_IPSR_PHYS(IP1SR2_31_28,	SDA6,		SEL_I2C6_3),
1047 
1048 	/* IP2SR2 */
1049 	PINMUX_IPSR_GPSR(IP2SR2_3_0,	FXR_TXDA_A),
1050 	PINMUX_IPSR_GPSR(IP2SR2_3_0,	MSIOF3_SS1),
1051 
1052 	PINMUX_IPSR_GPSR(IP2SR2_7_4,	RXDA_EXTFXR_A),
1053 	PINMUX_IPSR_GPSR(IP2SR2_7_4,	MSIOF3_SS2),
1054 	PINMUX_IPSR_GPSR(IP2SR2_7_4,	BS_N),
1055 
1056 	PINMUX_IPSR_GPSR(IP2SR2_11_8,	FXR_TXDB),
1057 	PINMUX_IPSR_GPSR(IP2SR2_11_8,	MSIOF3_RXD),
1058 	PINMUX_IPSR_GPSR(IP2SR2_11_8,	RD_N),
1059 
1060 	PINMUX_IPSR_GPSR(IP2SR2_15_12,	RXDB_EXTFXR),
1061 	PINMUX_IPSR_GPSR(IP2SR2_15_12,	MSIOF3_TXD),
1062 	PINMUX_IPSR_GPSR(IP2SR2_15_12,	WE0_N),
1063 
1064 	PINMUX_IPSR_GPSR(IP2SR2_19_16,	CLK_EXTFXR),
1065 	PINMUX_IPSR_GPSR(IP2SR2_19_16,	MSIOF3_SCK),
1066 	PINMUX_IPSR_GPSR(IP2SR2_19_16,	WE1_N),
1067 
1068 	PINMUX_IPSR_GPSR(IP2SR2_23_20,	TPU0TO0),
1069 	PINMUX_IPSR_GPSR(IP2SR2_23_20,	MSIOF3_SYNC),
1070 	PINMUX_IPSR_GPSR(IP2SR2_23_20,	RD_WR_N),
1071 
1072 	PINMUX_IPSR_GPSR(IP2SR2_27_24,	TPU0TO1),
1073 	PINMUX_IPSR_GPSR(IP2SR2_27_24,	CLKOUT),
1074 
1075 	PINMUX_IPSR_GPSR(IP2SR2_31_28,	TCLK1_A),
1076 	PINMUX_IPSR_GPSR(IP2SR2_31_28,	EX_WAIT0),
1077 
1078 	/* IP0SR3 */
1079 	PINMUX_IPSR_GPSR(IP0SR3_7_4,	CANFD0_TX),
1080 	PINMUX_IPSR_GPSR(IP0SR3_7_4,	FXR_TXDA_B),
1081 	PINMUX_IPSR_GPSR(IP0SR3_7_4,	TX1_B),
1082 
1083 	PINMUX_IPSR_GPSR(IP0SR3_11_8,	CANFD0_RX),
1084 	PINMUX_IPSR_GPSR(IP0SR3_11_8,	RXDA_EXTFXR_B),
1085 	PINMUX_IPSR_GPSR(IP0SR3_11_8,	RX1_B),
1086 
1087 	PINMUX_IPSR_GPSR(IP0SR3_23_20,	CANFD2_TX),
1088 	PINMUX_IPSR_GPSR(IP0SR3_23_20,	TPU0TO2),
1089 	PINMUX_IPSR_GPSR(IP0SR3_23_20,	PWM0),
1090 
1091 	PINMUX_IPSR_GPSR(IP0SR3_27_24,	CANFD2_RX),
1092 	PINMUX_IPSR_GPSR(IP0SR3_27_24,	TPU0TO3),
1093 	PINMUX_IPSR_GPSR(IP0SR3_27_24,	PWM1),
1094 
1095 	PINMUX_IPSR_GPSR(IP0SR3_31_28,	CANFD3_TX),
1096 	PINMUX_IPSR_GPSR(IP0SR3_31_28,	PWM2),
1097 
1098 	/* IP1SR3 */
1099 	PINMUX_IPSR_GPSR(IP1SR3_3_0,	CANFD3_RX),
1100 	PINMUX_IPSR_GPSR(IP1SR3_3_0,	PWM3),
1101 
1102 	PINMUX_IPSR_GPSR(IP1SR3_7_4,	CANFD4_TX),
1103 	PINMUX_IPSR_GPSR(IP1SR3_7_4,	PWM4),
1104 	PINMUX_IPSR_GPSR(IP1SR3_7_4,	FXR_CLKOUT1),
1105 
1106 	PINMUX_IPSR_GPSR(IP1SR3_11_8,	CANFD4_RX),
1107 	PINMUX_IPSR_GPSR(IP1SR3_11_8,	FXR_CLKOUT2),
1108 
1109 	PINMUX_IPSR_GPSR(IP1SR3_15_12,	CANFD5_TX),
1110 	PINMUX_IPSR_GPSR(IP1SR3_15_12,	FXR_TXENA_N),
1111 
1112 	PINMUX_IPSR_GPSR(IP1SR3_19_16,	CANFD5_RX),
1113 	PINMUX_IPSR_GPSR(IP1SR3_19_16,	FXR_TXENB_N),
1114 
1115 	PINMUX_IPSR_GPSR(IP1SR3_23_20,	CANFD6_TX),
1116 	PINMUX_IPSR_GPSR(IP1SR3_23_20,	STPWT_EXTFXR),
1117 
1118 	/* IP0SR4 */
1119 	PINMUX_IPSR_GPSR(IP0SR4_3_0,	AVB0_RX_CTL),
1120 	PINMUX_IPSR_GPSR(IP0SR4_3_0,	AVB0_MII_RX_DV),
1121 
1122 	PINMUX_IPSR_GPSR(IP0SR4_7_4,	AVB0_RXC),
1123 	PINMUX_IPSR_GPSR(IP0SR4_7_4,	AVB0_MII_RXC),
1124 
1125 	PINMUX_IPSR_GPSR(IP0SR4_11_8,	AVB0_RD0),
1126 	PINMUX_IPSR_GPSR(IP0SR4_11_8,	AVB0_MII_RD0),
1127 
1128 	PINMUX_IPSR_GPSR(IP0SR4_15_12,	AVB0_RD1),
1129 	PINMUX_IPSR_GPSR(IP0SR4_15_12,	AVB0_MII_RD1),
1130 
1131 	PINMUX_IPSR_GPSR(IP0SR4_19_16,	AVB0_RD2),
1132 	PINMUX_IPSR_GPSR(IP0SR4_19_16,	AVB0_MII_RD2),
1133 
1134 	PINMUX_IPSR_GPSR(IP0SR4_23_20,	AVB0_RD3),
1135 	PINMUX_IPSR_GPSR(IP0SR4_23_20,	AVB0_MII_RD3),
1136 
1137 	PINMUX_IPSR_GPSR(IP0SR4_27_24,	AVB0_TX_CTL),
1138 	PINMUX_IPSR_GPSR(IP0SR4_27_24,	AVB0_MII_TX_EN),
1139 
1140 	PINMUX_IPSR_GPSR(IP0SR4_31_28,	AVB0_TXC),
1141 	PINMUX_IPSR_GPSR(IP0SR4_31_28,	AVB0_MII_TXC),
1142 
1143 	/* IP1SR4 */
1144 	PINMUX_IPSR_GPSR(IP1SR4_3_0,	AVB0_TD0),
1145 	PINMUX_IPSR_GPSR(IP1SR4_3_0,	AVB0_MII_TD0),
1146 
1147 	PINMUX_IPSR_GPSR(IP1SR4_7_4,	AVB0_TD1),
1148 	PINMUX_IPSR_GPSR(IP1SR4_7_4,	AVB0_MII_TD1),
1149 
1150 	PINMUX_IPSR_GPSR(IP1SR4_11_8,	AVB0_TD2),
1151 	PINMUX_IPSR_GPSR(IP1SR4_11_8,	AVB0_MII_TD2),
1152 
1153 	PINMUX_IPSR_GPSR(IP1SR4_15_12,	AVB0_TD3),
1154 	PINMUX_IPSR_GPSR(IP1SR4_15_12,	AVB0_MII_TD3),
1155 
1156 	PINMUX_IPSR_GPSR(IP1SR4_19_16,	AVB0_TXCREFCLK),
1157 
1158 	PINMUX_IPSR_GPSR(IP1SR4_23_20,	AVB0_MDIO),
1159 
1160 	PINMUX_IPSR_GPSR(IP1SR4_27_24,	AVB0_MDC),
1161 
1162 	PINMUX_IPSR_GPSR(IP1SR4_31_28,	AVB0_MAGIC),
1163 
1164 	/* IP2SR4 */
1165 	PINMUX_IPSR_GPSR(IP2SR4_7_4,	AVB0_LINK),
1166 	PINMUX_IPSR_GPSR(IP2SR4_7_4,	AVB0_MII_TX_ER),
1167 
1168 	PINMUX_IPSR_GPSR(IP2SR4_11_8,	AVB0_AVTP_MATCH),
1169 	PINMUX_IPSR_GPSR(IP2SR4_11_8,	AVB0_MII_RX_ER),
1170 	PINMUX_IPSR_GPSR(IP2SR4_11_8,	CC5_OSCOUT),
1171 
1172 	PINMUX_IPSR_GPSR(IP2SR4_15_12,	AVB0_AVTP_CAPTURE),
1173 	PINMUX_IPSR_GPSR(IP2SR4_15_12,	AVB0_MII_CRS),
1174 
1175 	PINMUX_IPSR_GPSR(IP2SR4_19_16,	AVB0_AVTP_PPS),
1176 	PINMUX_IPSR_GPSR(IP2SR4_19_16,	AVB0_MII_COL),
1177 
1178 	/* IP0SR5 */
1179 	PINMUX_IPSR_GPSR(IP0SR5_3_0,	AVB1_RX_CTL),
1180 	PINMUX_IPSR_GPSR(IP0SR5_3_0,	AVB1_MII_RX_DV),
1181 
1182 	PINMUX_IPSR_GPSR(IP0SR5_7_4,	AVB1_RXC),
1183 	PINMUX_IPSR_GPSR(IP0SR5_7_4,	AVB1_MII_RXC),
1184 
1185 	PINMUX_IPSR_GPSR(IP0SR5_11_8,	AVB1_RD0),
1186 	PINMUX_IPSR_GPSR(IP0SR5_11_8,	AVB1_MII_RD0),
1187 
1188 	PINMUX_IPSR_GPSR(IP0SR5_15_12,	AVB1_RD1),
1189 	PINMUX_IPSR_GPSR(IP0SR5_15_12,	AVB1_MII_RD1),
1190 
1191 	PINMUX_IPSR_GPSR(IP0SR5_19_16,	AVB1_RD2),
1192 	PINMUX_IPSR_GPSR(IP0SR5_19_16,	AVB1_MII_RD2),
1193 
1194 	PINMUX_IPSR_GPSR(IP0SR5_23_20,	AVB1_RD3),
1195 	PINMUX_IPSR_GPSR(IP0SR5_23_20,	AVB1_MII_RD3),
1196 
1197 	PINMUX_IPSR_GPSR(IP0SR5_27_24,	AVB1_TX_CTL),
1198 	PINMUX_IPSR_GPSR(IP0SR5_27_24,	AVB1_MII_TX_EN),
1199 
1200 	PINMUX_IPSR_GPSR(IP0SR5_31_28,	AVB1_TXC),
1201 	PINMUX_IPSR_GPSR(IP0SR5_31_28,	AVB1_MII_TXC),
1202 
1203 	/* IP1SR5 */
1204 	PINMUX_IPSR_GPSR(IP1SR5_3_0,	AVB1_TD0),
1205 	PINMUX_IPSR_GPSR(IP1SR5_3_0,	AVB1_MII_TD0),
1206 
1207 	PINMUX_IPSR_GPSR(IP1SR5_7_4,	AVB1_TD1),
1208 	PINMUX_IPSR_GPSR(IP1SR5_7_4,	AVB1_MII_TD1),
1209 
1210 	PINMUX_IPSR_GPSR(IP1SR5_11_8,	AVB1_TD2),
1211 	PINMUX_IPSR_GPSR(IP1SR5_11_8,	AVB1_MII_TD2),
1212 
1213 	PINMUX_IPSR_GPSR(IP1SR5_15_12,	AVB1_TD3),
1214 	PINMUX_IPSR_GPSR(IP1SR5_15_12,	AVB1_MII_TD3),
1215 
1216 	PINMUX_IPSR_GPSR(IP1SR5_19_16,	AVB1_TXCREFCLK),
1217 
1218 	PINMUX_IPSR_GPSR(IP1SR5_23_20,	AVB1_MDIO),
1219 
1220 	PINMUX_IPSR_GPSR(IP1SR5_27_24,	AVB1_MDC),
1221 
1222 	PINMUX_IPSR_GPSR(IP1SR5_31_28,	AVB1_MAGIC),
1223 
1224 	/* IP2SR5 */
1225 	PINMUX_IPSR_GPSR(IP2SR5_7_4,	AVB1_LINK),
1226 	PINMUX_IPSR_GPSR(IP2SR5_7_4,	AVB1_MII_TX_ER),
1227 
1228 	PINMUX_IPSR_GPSR(IP2SR5_11_8,	AVB1_AVTP_MATCH),
1229 	PINMUX_IPSR_GPSR(IP2SR5_11_8,	AVB1_MII_RX_ER),
1230 
1231 	PINMUX_IPSR_GPSR(IP2SR5_15_12,	AVB1_AVTP_CAPTURE),
1232 	PINMUX_IPSR_GPSR(IP2SR5_15_12,	AVB1_MII_CRS),
1233 
1234 	PINMUX_IPSR_GPSR(IP2SR5_19_16,	AVB1_AVTP_PPS),
1235 	PINMUX_IPSR_GPSR(IP2SR5_19_16,	AVB1_MII_COL),
1236 };
1237 
1238 /*
1239  * Pins not associated with a GPIO port.
1240  */
1241 enum {
1242 	GP_ASSIGN_LAST(),
1243 	NOGP_ALL(),
1244 };
1245 
1246 static const struct sh_pfc_pin pinmux_pins[] = {
1247 	PINMUX_GPIO_GP_ALL(),
1248 };
1249 
1250 /* - AVB0 ------------------------------------------------ */
1251 static const unsigned int avb0_link_pins[] = {
1252 	/* AVB0_LINK */
1253 	RCAR_GP_PIN(4, 17),
1254 };
1255 static const unsigned int avb0_link_mux[] = {
1256 	AVB0_LINK_MARK,
1257 };
1258 static const unsigned int avb0_magic_pins[] = {
1259 	/* AVB0_MAGIC */
1260 	RCAR_GP_PIN(4, 15),
1261 };
1262 static const unsigned int avb0_magic_mux[] = {
1263 	AVB0_MAGIC_MARK,
1264 };
1265 static const unsigned int avb0_phy_int_pins[] = {
1266 	/* AVB0_PHY_INT */
1267 	RCAR_GP_PIN(4, 16),
1268 };
1269 static const unsigned int avb0_phy_int_mux[] = {
1270 	AVB0_PHY_INT_MARK,
1271 };
1272 static const unsigned int avb0_mdio_pins[] = {
1273 	/* AVB0_MDC, AVB0_MDIO */
1274 	RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1275 };
1276 static const unsigned int avb0_mdio_mux[] = {
1277 	AVB0_MDC_MARK, AVB0_MDIO_MARK,
1278 };
1279 static const unsigned int avb0_rgmii_pins[] = {
1280 	/*
1281 	 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
1282 	 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
1283 	 */
1284 	RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1285 	RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1286 	RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1287 	RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1288 	RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1289 	RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1290 };
1291 static const unsigned int avb0_rgmii_mux[] = {
1292 	AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
1293 	AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
1294 	AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
1295 	AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
1296 };
1297 static const unsigned int avb0_txcrefclk_pins[] = {
1298 	/* AVB0_TXCREFCLK */
1299 	RCAR_GP_PIN(4, 12),
1300 };
1301 static const unsigned int avb0_txcrefclk_mux[] = {
1302 	AVB0_TXCREFCLK_MARK,
1303 };
1304 static const unsigned int avb0_avtp_pps_pins[] = {
1305 	/* AVB0_AVTP_PPS */
1306 	RCAR_GP_PIN(4, 20),
1307 };
1308 static const unsigned int avb0_avtp_pps_mux[] = {
1309 	AVB0_AVTP_PPS_MARK,
1310 };
1311 static const unsigned int avb0_avtp_capture_pins[] = {
1312 	/* AVB0_AVTP_CAPTURE */
1313 	RCAR_GP_PIN(4, 19),
1314 };
1315 static const unsigned int avb0_avtp_capture_mux[] = {
1316 	AVB0_AVTP_CAPTURE_MARK,
1317 };
1318 static const unsigned int avb0_avtp_match_pins[] = {
1319 	/* AVB0_AVTP_MATCH */
1320 	RCAR_GP_PIN(4, 18),
1321 };
1322 static const unsigned int avb0_avtp_match_mux[] = {
1323 	AVB0_AVTP_MATCH_MARK,
1324 };
1325 
1326 /* - AVB1 ------------------------------------------------ */
1327 static const unsigned int avb1_link_pins[] = {
1328 	/* AVB1_LINK */
1329 	RCAR_GP_PIN(5, 17),
1330 };
1331 static const unsigned int avb1_link_mux[] = {
1332 	AVB1_LINK_MARK,
1333 };
1334 static const unsigned int avb1_magic_pins[] = {
1335 	/* AVB1_MAGIC */
1336 	RCAR_GP_PIN(5, 15),
1337 };
1338 static const unsigned int avb1_magic_mux[] = {
1339 	AVB1_MAGIC_MARK,
1340 };
1341 static const unsigned int avb1_phy_int_pins[] = {
1342 	/* AVB1_PHY_INT */
1343 	RCAR_GP_PIN(5, 16),
1344 };
1345 static const unsigned int avb1_phy_int_mux[] = {
1346 	AVB1_PHY_INT_MARK,
1347 };
1348 static const unsigned int avb1_mdio_pins[] = {
1349 	/* AVB1_MDC, AVB1_MDIO */
1350 	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13),
1351 };
1352 static const unsigned int avb1_mdio_mux[] = {
1353 	AVB1_MDC_MARK, AVB1_MDIO_MARK,
1354 };
1355 static const unsigned int avb1_rgmii_pins[] = {
1356 	/*
1357 	 * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
1358 	 * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
1359 	 */
1360 	RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1361 	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1362 	RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1363 	RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
1364 	RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1365 	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1366 };
1367 static const unsigned int avb1_rgmii_mux[] = {
1368 	AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
1369 	AVB1_TD0_MARK, AVB1_TD1_MARK, AVB1_TD2_MARK, AVB1_TD3_MARK,
1370 	AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
1371 	AVB1_RD0_MARK, AVB1_RD1_MARK, AVB1_RD2_MARK, AVB1_RD3_MARK,
1372 };
1373 static const unsigned int avb1_txcrefclk_pins[] = {
1374 	/* AVB1_TXCREFCLK */
1375 	RCAR_GP_PIN(5, 12),
1376 };
1377 static const unsigned int avb1_txcrefclk_mux[] = {
1378 	AVB1_TXCREFCLK_MARK,
1379 };
1380 static const unsigned int avb1_avtp_pps_pins[] = {
1381 	/* AVB1_AVTP_PPS */
1382 	RCAR_GP_PIN(5, 20),
1383 };
1384 static const unsigned int avb1_avtp_pps_mux[] = {
1385 	AVB1_AVTP_PPS_MARK,
1386 };
1387 static const unsigned int avb1_avtp_capture_pins[] = {
1388 	/* AVB1_AVTP_CAPTURE */
1389 	RCAR_GP_PIN(5, 19),
1390 };
1391 static const unsigned int avb1_avtp_capture_mux[] = {
1392 	AVB1_AVTP_CAPTURE_MARK,
1393 };
1394 static const unsigned int avb1_avtp_match_pins[] = {
1395 	/* AVB1_AVTP_MATCH */
1396 	RCAR_GP_PIN(5, 18),
1397 };
1398 static const unsigned int avb1_avtp_match_mux[] = {
1399 	AVB1_AVTP_MATCH_MARK,
1400 };
1401 
1402 /* - AVB2 ------------------------------------------------ */
1403 static const unsigned int avb2_link_pins[] = {
1404 	/* AVB2_LINK */
1405 	RCAR_GP_PIN(6, 17),
1406 };
1407 static const unsigned int avb2_link_mux[] = {
1408 	AVB2_LINK_MARK,
1409 };
1410 static const unsigned int avb2_magic_pins[] = {
1411 	/* AVB2_MAGIC */
1412 	RCAR_GP_PIN(6, 15),
1413 };
1414 static const unsigned int avb2_magic_mux[] = {
1415 	AVB2_MAGIC_MARK,
1416 };
1417 static const unsigned int avb2_phy_int_pins[] = {
1418 	/* AVB2_PHY_INT */
1419 	RCAR_GP_PIN(6, 16),
1420 };
1421 static const unsigned int avb2_phy_int_mux[] = {
1422 	AVB2_PHY_INT_MARK,
1423 };
1424 static const unsigned int avb2_mdio_pins[] = {
1425 	/* AVB2_MDC, AVB2_MDIO */
1426 	RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13),
1427 };
1428 static const unsigned int avb2_mdio_mux[] = {
1429 	AVB2_MDC_MARK, AVB2_MDIO_MARK,
1430 };
1431 static const unsigned int avb2_rgmii_pins[] = {
1432 	/*
1433 	 * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
1434 	 * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
1435 	 */
1436 	RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1437 	RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1438 	RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1439 	RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
1440 	RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1441 	RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1442 };
1443 static const unsigned int avb2_rgmii_mux[] = {
1444 	AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
1445 	AVB2_TD0_MARK, AVB2_TD1_MARK, AVB2_TD2_MARK, AVB2_TD3_MARK,
1446 	AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
1447 	AVB2_RD0_MARK, AVB2_RD1_MARK, AVB2_RD2_MARK, AVB2_RD3_MARK,
1448 };
1449 static const unsigned int avb2_txcrefclk_pins[] = {
1450 	/* AVB2_TXCREFCLK */
1451 	RCAR_GP_PIN(6, 12),
1452 };
1453 static const unsigned int avb2_txcrefclk_mux[] = {
1454 	AVB2_TXCREFCLK_MARK,
1455 };
1456 static const unsigned int avb2_avtp_pps_pins[] = {
1457 	/* AVB2_AVTP_PPS */
1458 	RCAR_GP_PIN(6, 20),
1459 };
1460 static const unsigned int avb2_avtp_pps_mux[] = {
1461 	AVB2_AVTP_PPS_MARK,
1462 };
1463 static const unsigned int avb2_avtp_capture_pins[] = {
1464 	/* AVB2_AVTP_CAPTURE */
1465 	RCAR_GP_PIN(6, 19),
1466 };
1467 static const unsigned int avb2_avtp_capture_mux[] = {
1468 	AVB2_AVTP_CAPTURE_MARK,
1469 };
1470 static const unsigned int avb2_avtp_match_pins[] = {
1471 	/* AVB2_AVTP_MATCH */
1472 	RCAR_GP_PIN(6, 18),
1473 };
1474 static const unsigned int avb2_avtp_match_mux[] = {
1475 	AVB2_AVTP_MATCH_MARK,
1476 };
1477 
1478 /* - AVB3 ------------------------------------------------ */
1479 static const unsigned int avb3_link_pins[] = {
1480 	/* AVB3_LINK */
1481 	RCAR_GP_PIN(7, 17),
1482 };
1483 static const unsigned int avb3_link_mux[] = {
1484 	AVB3_LINK_MARK,
1485 };
1486 static const unsigned int avb3_magic_pins[] = {
1487 	/* AVB3_MAGIC */
1488 	RCAR_GP_PIN(7, 15),
1489 };
1490 static const unsigned int avb3_magic_mux[] = {
1491 	AVB3_MAGIC_MARK,
1492 };
1493 static const unsigned int avb3_phy_int_pins[] = {
1494 	/* AVB3_PHY_INT */
1495 	RCAR_GP_PIN(7, 16),
1496 };
1497 static const unsigned int avb3_phy_int_mux[] = {
1498 	AVB3_PHY_INT_MARK,
1499 };
1500 static const unsigned int avb3_mdio_pins[] = {
1501 	/* AVB3_MDC, AVB3_MDIO */
1502 	RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13),
1503 };
1504 static const unsigned int avb3_mdio_mux[] = {
1505 	AVB3_MDC_MARK, AVB3_MDIO_MARK,
1506 };
1507 static const unsigned int avb3_rgmii_pins[] = {
1508 	/*
1509 	 * AVB3_TX_CTL, AVB3_TXC, AVB3_TD0, AVB3_TD1, AVB3_TD2, AVB3_TD3,
1510 	 * AVB3_RX_CTL, AVB3_RXC, AVB3_RD0, AVB3_RD1, AVB3_RD2, AVB3_RD3,
1511 	 */
1512 	RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1513 	RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1514 	RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1515 	RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1),
1516 	RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1517 	RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1518 };
1519 static const unsigned int avb3_rgmii_mux[] = {
1520 	AVB3_TX_CTL_MARK, AVB3_TXC_MARK,
1521 	AVB3_TD0_MARK, AVB3_TD1_MARK, AVB3_TD2_MARK, AVB3_TD3_MARK,
1522 	AVB3_RX_CTL_MARK, AVB3_RXC_MARK,
1523 	AVB3_RD0_MARK, AVB3_RD1_MARK, AVB3_RD2_MARK, AVB3_RD3_MARK,
1524 };
1525 static const unsigned int avb3_txcrefclk_pins[] = {
1526 	/* AVB3_TXCREFCLK */
1527 	RCAR_GP_PIN(7, 12),
1528 };
1529 static const unsigned int avb3_txcrefclk_mux[] = {
1530 	AVB3_TXCREFCLK_MARK,
1531 };
1532 static const unsigned int avb3_avtp_pps_pins[] = {
1533 	/* AVB3_AVTP_PPS */
1534 	RCAR_GP_PIN(7, 20),
1535 };
1536 static const unsigned int avb3_avtp_pps_mux[] = {
1537 	AVB3_AVTP_PPS_MARK,
1538 };
1539 static const unsigned int avb3_avtp_capture_pins[] = {
1540 	/* AVB3_AVTP_CAPTURE */
1541 	RCAR_GP_PIN(7, 19),
1542 };
1543 static const unsigned int avb3_avtp_capture_mux[] = {
1544 	AVB3_AVTP_CAPTURE_MARK,
1545 };
1546 static const unsigned int avb3_avtp_match_pins[] = {
1547 	/* AVB3_AVTP_MATCH */
1548 	RCAR_GP_PIN(7, 18),
1549 };
1550 static const unsigned int avb3_avtp_match_mux[] = {
1551 	AVB3_AVTP_MATCH_MARK,
1552 };
1553 
1554 /* - AVB4 ------------------------------------------------ */
1555 static const unsigned int avb4_link_pins[] = {
1556 	/* AVB4_LINK */
1557 	RCAR_GP_PIN(8, 17),
1558 };
1559 static const unsigned int avb4_link_mux[] = {
1560 	AVB4_LINK_MARK,
1561 };
1562 static const unsigned int avb4_magic_pins[] = {
1563 	/* AVB4_MAGIC */
1564 	RCAR_GP_PIN(8, 15),
1565 };
1566 static const unsigned int avb4_magic_mux[] = {
1567 	AVB4_MAGIC_MARK,
1568 };
1569 static const unsigned int avb4_phy_int_pins[] = {
1570 	/* AVB4_PHY_INT */
1571 	RCAR_GP_PIN(8, 16),
1572 };
1573 static const unsigned int avb4_phy_int_mux[] = {
1574 	AVB4_PHY_INT_MARK,
1575 };
1576 static const unsigned int avb4_mdio_pins[] = {
1577 	/* AVB4_MDC, AVB4_MDIO */
1578 	RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13),
1579 };
1580 static const unsigned int avb4_mdio_mux[] = {
1581 	AVB4_MDC_MARK, AVB4_MDIO_MARK,
1582 };
1583 static const unsigned int avb4_rgmii_pins[] = {
1584 	/*
1585 	 * AVB4_TX_CTL, AVB4_TXC, AVB4_TD0, AVB4_TD1, AVB4_TD2, AVB4_TD3,
1586 	 * AVB4_RX_CTL, AVB4_RXC, AVB4_RD0, AVB4_RD1, AVB4_RD2, AVB4_RD3,
1587 	 */
1588 	RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1589 	RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1590 	RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1591 	RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1),
1592 	RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1593 	RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1594 };
1595 static const unsigned int avb4_rgmii_mux[] = {
1596 	AVB4_TX_CTL_MARK, AVB4_TXC_MARK,
1597 	AVB4_TD0_MARK, AVB4_TD1_MARK, AVB4_TD2_MARK, AVB4_TD3_MARK,
1598 	AVB4_RX_CTL_MARK, AVB4_RXC_MARK,
1599 	AVB4_RD0_MARK, AVB4_RD1_MARK, AVB4_RD2_MARK, AVB4_RD3_MARK,
1600 };
1601 static const unsigned int avb4_txcrefclk_pins[] = {
1602 	/* AVB4_TXCREFCLK */
1603 	RCAR_GP_PIN(8, 12),
1604 };
1605 static const unsigned int avb4_txcrefclk_mux[] = {
1606 	AVB4_TXCREFCLK_MARK,
1607 };
1608 static const unsigned int avb4_avtp_pps_pins[] = {
1609 	/* AVB4_AVTP_PPS */
1610 	RCAR_GP_PIN(8, 20),
1611 };
1612 static const unsigned int avb4_avtp_pps_mux[] = {
1613 	AVB4_AVTP_PPS_MARK,
1614 };
1615 static const unsigned int avb4_avtp_capture_pins[] = {
1616 	/* AVB4_AVTP_CAPTURE */
1617 	RCAR_GP_PIN(8, 19),
1618 };
1619 static const unsigned int avb4_avtp_capture_mux[] = {
1620 	AVB4_AVTP_CAPTURE_MARK,
1621 };
1622 static const unsigned int avb4_avtp_match_pins[] = {
1623 	/* AVB4_AVTP_MATCH */
1624 	RCAR_GP_PIN(8, 18),
1625 };
1626 static const unsigned int avb4_avtp_match_mux[] = {
1627 	AVB4_AVTP_MATCH_MARK,
1628 };
1629 
1630 /* - AVB5 ------------------------------------------------ */
1631 static const unsigned int avb5_link_pins[] = {
1632 	/* AVB5_LINK */
1633 	RCAR_GP_PIN(9, 17),
1634 };
1635 static const unsigned int avb5_link_mux[] = {
1636 	AVB5_LINK_MARK,
1637 };
1638 static const unsigned int avb5_magic_pins[] = {
1639 	/* AVB5_MAGIC */
1640 	RCAR_GP_PIN(9, 15),
1641 };
1642 static const unsigned int avb5_magic_mux[] = {
1643 	AVB5_MAGIC_MARK,
1644 };
1645 static const unsigned int avb5_phy_int_pins[] = {
1646 	/* AVB5_PHY_INT */
1647 	RCAR_GP_PIN(9, 16),
1648 };
1649 static const unsigned int avb5_phy_int_mux[] = {
1650 	AVB5_PHY_INT_MARK,
1651 };
1652 static const unsigned int avb5_mdio_pins[] = {
1653 	/* AVB5_MDC, AVB5_MDIO */
1654 	RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13),
1655 };
1656 static const unsigned int avb5_mdio_mux[] = {
1657 	AVB5_MDC_MARK, AVB5_MDIO_MARK,
1658 };
1659 static const unsigned int avb5_rgmii_pins[] = {
1660 	/*
1661 	 * AVB5_TX_CTL, AVB5_TXC, AVB5_TD0, AVB5_TD1, AVB5_TD2, AVB5_TD3,
1662 	 * AVB5_RX_CTL, AVB5_RXC, AVB5_RD0, AVB5_RD1, AVB5_RD2, AVB5_RD3,
1663 	 */
1664 	RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1665 	RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1666 	RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1667 	RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1),
1668 	RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1669 	RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1670 };
1671 static const unsigned int avb5_rgmii_mux[] = {
1672 	AVB5_TX_CTL_MARK, AVB5_TXC_MARK,
1673 	AVB5_TD0_MARK, AVB5_TD1_MARK, AVB5_TD2_MARK, AVB5_TD3_MARK,
1674 	AVB5_RX_CTL_MARK, AVB5_RXC_MARK,
1675 	AVB5_RD0_MARK, AVB5_RD1_MARK, AVB5_RD2_MARK, AVB5_RD3_MARK,
1676 };
1677 static const unsigned int avb5_txcrefclk_pins[] = {
1678 	/* AVB5_TXCREFCLK */
1679 	RCAR_GP_PIN(9, 12),
1680 };
1681 static const unsigned int avb5_txcrefclk_mux[] = {
1682 	AVB5_TXCREFCLK_MARK,
1683 };
1684 static const unsigned int avb5_avtp_pps_pins[] = {
1685 	/* AVB5_AVTP_PPS */
1686 	RCAR_GP_PIN(9, 20),
1687 };
1688 static const unsigned int avb5_avtp_pps_mux[] = {
1689 	AVB5_AVTP_PPS_MARK,
1690 };
1691 static const unsigned int avb5_avtp_capture_pins[] = {
1692 	/* AVB5_AVTP_CAPTURE */
1693 	RCAR_GP_PIN(9, 19),
1694 };
1695 static const unsigned int avb5_avtp_capture_mux[] = {
1696 	AVB5_AVTP_CAPTURE_MARK,
1697 };
1698 static const unsigned int avb5_avtp_match_pins[] = {
1699 	/* AVB5_AVTP_MATCH */
1700 	RCAR_GP_PIN(9, 18),
1701 };
1702 static const unsigned int avb5_avtp_match_mux[] = {
1703 	AVB5_AVTP_MATCH_MARK,
1704 };
1705 
1706 /* - CANFD0 ----------------------------------------------------------------- */
1707 static const unsigned int canfd0_data_pins[] = {
1708 	/* CANFD0_TX, CANFD0_RX */
1709 	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1710 };
1711 static const unsigned int canfd0_data_mux[] = {
1712 	CANFD0_TX_MARK, CANFD0_RX_MARK,
1713 };
1714 
1715 /* - CANFD1 ----------------------------------------------------------------- */
1716 static const unsigned int canfd1_data_pins[] = {
1717 	/* CANFD1_TX, CANFD1_RX */
1718 	RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1719 };
1720 static const unsigned int canfd1_data_mux[] = {
1721 	CANFD1_TX_MARK, CANFD1_RX_MARK,
1722 };
1723 
1724 /* - CANFD2 ----------------------------------------------------------------- */
1725 static const unsigned int canfd2_data_pins[] = {
1726 	/* CANFD2_TX, CANFD2_RX */
1727 	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
1728 };
1729 static const unsigned int canfd2_data_mux[] = {
1730 	CANFD2_TX_MARK, CANFD2_RX_MARK,
1731 };
1732 
1733 /* - CANFD3 ----------------------------------------------------------------- */
1734 static const unsigned int canfd3_data_pins[] = {
1735 	/* CANFD3_TX, CANFD3_RX */
1736 	RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
1737 };
1738 static const unsigned int canfd3_data_mux[] = {
1739 	CANFD3_TX_MARK, CANFD3_RX_MARK,
1740 };
1741 
1742 /* - CANFD4 ----------------------------------------------------------------- */
1743 static const unsigned int canfd4_data_pins[] = {
1744 	/* CANFD4_TX, CANFD4_RX */
1745 	RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1746 };
1747 static const unsigned int canfd4_data_mux[] = {
1748 	CANFD4_TX_MARK, CANFD4_RX_MARK,
1749 };
1750 
1751 /* - CANFD5 ----------------------------------------------------------------- */
1752 static const unsigned int canfd5_data_pins[] = {
1753 	/* CANFD5_TX, CANFD5_RX */
1754 	RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1755 };
1756 static const unsigned int canfd5_data_mux[] = {
1757 	CANFD5_TX_MARK, CANFD5_RX_MARK,
1758 };
1759 
1760 /* - CANFD6 ----------------------------------------------------------------- */
1761 static const unsigned int canfd6_data_pins[] = {
1762 	/* CANFD6_TX, CANFD6_RX */
1763 	RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1764 };
1765 static const unsigned int canfd6_data_mux[] = {
1766 	CANFD6_TX_MARK, CANFD6_RX_MARK,
1767 };
1768 
1769 /* - CANFD7 ----------------------------------------------------------------- */
1770 static const unsigned int canfd7_data_pins[] = {
1771 	/* CANFD7_TX, CANFD7_RX */
1772 	RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1773 };
1774 static const unsigned int canfd7_data_mux[] = {
1775 	CANFD7_TX_MARK, CANFD7_RX_MARK,
1776 };
1777 
1778 /* - CANFD Clock ------------------------------------------------------------ */
1779 static const unsigned int can_clk_pins[] = {
1780 	/* CAN_CLK */
1781 	RCAR_GP_PIN(3, 0),
1782 };
1783 static const unsigned int can_clk_mux[] = {
1784 	CAN_CLK_MARK,
1785 };
1786 
1787 /* - DU --------------------------------------------------------------------- */
1788 static const unsigned int du_rgb888_pins[] = {
1789 	/* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
1790 	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1791 	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1792 	RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
1793 	RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
1794 	RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1795 	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1796 };
1797 static const unsigned int du_rgb888_mux[] = {
1798 	DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
1799 	DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
1800 	DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
1801 	DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
1802 	DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
1803 	DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
1804 };
1805 static const unsigned int du_clk_out_pins[] = {
1806 	/* DU_DOTCLKOUT */
1807 	RCAR_GP_PIN(1, 24),
1808 };
1809 static const unsigned int du_clk_out_mux[] = {
1810 	DU_DOTCLKOUT_MARK,
1811 };
1812 static const unsigned int du_sync_pins[] = {
1813 	/* DU_HSYNC, DU_VSYNC */
1814 	RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 26),
1815 };
1816 static const unsigned int du_sync_mux[] = {
1817 	DU_HSYNC_MARK, DU_VSYNC_MARK,
1818 };
1819 static const unsigned int du_oddf_pins[] = {
1820 	/* DU_EXODDF/DU_ODDF/DISP/CDE */
1821 	RCAR_GP_PIN(1, 27),
1822 };
1823 static const unsigned int du_oddf_mux[] = {
1824 	DU_ODDF_DISP_CDE_MARK,
1825 };
1826 
1827 /* - HSCIF0 ----------------------------------------------------------------- */
1828 static const unsigned int hscif0_data_pins[] = {
1829 	/* HRX0, HTX0 */
1830 	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
1831 };
1832 static const unsigned int hscif0_data_mux[] = {
1833 	HRX0_MARK, HTX0_MARK,
1834 };
1835 static const unsigned int hscif0_clk_pins[] = {
1836 	/* HSCK0 */
1837 	RCAR_GP_PIN(1, 2),
1838 };
1839 static const unsigned int hscif0_clk_mux[] = {
1840 	HSCK0_MARK,
1841 };
1842 static const unsigned int hscif0_ctrl_pins[] = {
1843 	/* HRTS0#, HCTS0# */
1844 	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
1845 };
1846 static const unsigned int hscif0_ctrl_mux[] = {
1847 	HRTS0_N_MARK, HCTS0_N_MARK,
1848 };
1849 
1850 /* - HSCIF1 ----------------------------------------------------------------- */
1851 static const unsigned int hscif1_data_pins[] = {
1852 	/* HRX1, HTX1 */
1853 	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
1854 };
1855 static const unsigned int hscif1_data_mux[] = {
1856 	HRX1_MARK, HTX1_MARK,
1857 };
1858 static const unsigned int hscif1_clk_pins[] = {
1859 	/* HSCK1 */
1860 	RCAR_GP_PIN(1, 18),
1861 };
1862 static const unsigned int hscif1_clk_mux[] = {
1863 	HSCK1_MARK,
1864 };
1865 static const unsigned int hscif1_ctrl_pins[] = {
1866 	/* HRTS1#, HCTS1# */
1867 	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
1868 };
1869 static const unsigned int hscif1_ctrl_mux[] = {
1870 	HRTS1_N_MARK, HCTS1_N_MARK,
1871 };
1872 
1873 /* - HSCIF2 ----------------------------------------------------------------- */
1874 static const unsigned int hscif2_data_pins[] = {
1875 	/* HRX2, HTX2 */
1876 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1877 };
1878 static const unsigned int hscif2_data_mux[] = {
1879 	HRX2_MARK, HTX2_MARK,
1880 };
1881 static const unsigned int hscif2_clk_pins[] = {
1882 	/* HSCK2 */
1883 	RCAR_GP_PIN(2, 5),
1884 };
1885 static const unsigned int hscif2_clk_mux[] = {
1886 	HSCK2_MARK,
1887 };
1888 static const unsigned int hscif2_ctrl_pins[] = {
1889 	/* HRTS2#, HCTS2# */
1890 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
1891 };
1892 static const unsigned int hscif2_ctrl_mux[] = {
1893 	HRTS2_N_MARK, HCTS2_N_MARK,
1894 };
1895 
1896 /* - HSCIF3 ----------------------------------------------------------------- */
1897 static const unsigned int hscif3_data_pins[] = {
1898 	/* HRX3, HTX3 */
1899 	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17),
1900 };
1901 static const unsigned int hscif3_data_mux[] = {
1902 	HRX3_MARK, HTX3_MARK,
1903 };
1904 static const unsigned int hscif3_clk_pins[] = {
1905 	/* HSCK3 */
1906 	RCAR_GP_PIN(1, 14),
1907 };
1908 static const unsigned int hscif3_clk_mux[] = {
1909 	HSCK3_MARK,
1910 };
1911 static const unsigned int hscif3_ctrl_pins[] = {
1912 	/* HRTS3#, HCTS3# */
1913 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
1914 };
1915 static const unsigned int hscif3_ctrl_mux[] = {
1916 	HRTS3_N_MARK, HCTS3_N_MARK,
1917 };
1918 
1919 /* - I2C0 ------------------------------------------------------------------- */
1920 static const unsigned int i2c0_pins[] = {
1921 	/* SDA0, SCL0 */
1922 	RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1923 };
1924 static const unsigned int i2c0_mux[] = {
1925 	SDA0_MARK, SCL0_MARK,
1926 };
1927 
1928 /* - I2C1 ------------------------------------------------------------------- */
1929 static const unsigned int i2c1_pins[] = {
1930 	/* SDA1, SCL1 */
1931 	RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1932 };
1933 static const unsigned int i2c1_mux[] = {
1934 	SDA1_MARK, SCL1_MARK,
1935 };
1936 
1937 /* - I2C2 ------------------------------------------------------------------- */
1938 static const unsigned int i2c2_pins[] = {
1939 	/* SDA2, SCL2 */
1940 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
1941 };
1942 static const unsigned int i2c2_mux[] = {
1943 	SDA2_MARK, SCL2_MARK,
1944 };
1945 
1946 /* - I2C3 ------------------------------------------------------------------- */
1947 static const unsigned int i2c3_pins[] = {
1948 	/* SDA3, SCL3 */
1949 	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
1950 };
1951 static const unsigned int i2c3_mux[] = {
1952 	SDA3_MARK, SCL3_MARK,
1953 };
1954 
1955 /* - I2C4 ------------------------------------------------------------------- */
1956 static const unsigned int i2c4_pins[] = {
1957 	/* SDA4, SCL4 */
1958 	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1959 };
1960 static const unsigned int i2c4_mux[] = {
1961 	SDA4_MARK, SCL4_MARK,
1962 };
1963 
1964 /* - I2C5 ------------------------------------------------------------------- */
1965 static const unsigned int i2c5_pins[] = {
1966 	/* SDA5, SCL5 */
1967 	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
1968 };
1969 static const unsigned int i2c5_mux[] = {
1970 	SDA5_MARK, SCL5_MARK,
1971 };
1972 
1973 /* - I2C6 ------------------------------------------------------------------- */
1974 static const unsigned int i2c6_pins[] = {
1975 	/* SDA6, SCL6 */
1976 	RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14),
1977 };
1978 static const unsigned int i2c6_mux[] = {
1979 	SDA6_MARK, SCL6_MARK,
1980 };
1981 
1982 /* - INTC-EX ---------------------------------------------------------------- */
1983 static const unsigned int intc_ex_irq0_pins[] = {
1984 	/* IRQ0 */
1985 	RCAR_GP_PIN(1, 24),
1986 };
1987 static const unsigned int intc_ex_irq0_mux[] = {
1988 	IRQ0_MARK,
1989 };
1990 static const unsigned int intc_ex_irq1_pins[] = {
1991 	/* IRQ1 */
1992 	RCAR_GP_PIN(1, 25),
1993 };
1994 static const unsigned int intc_ex_irq1_mux[] = {
1995 	IRQ1_MARK,
1996 };
1997 static const unsigned int intc_ex_irq2_pins[] = {
1998 	/* IRQ2 */
1999 	RCAR_GP_PIN(1, 26),
2000 };
2001 static const unsigned int intc_ex_irq2_mux[] = {
2002 	IRQ2_MARK,
2003 };
2004 static const unsigned int intc_ex_irq3_pins[] = {
2005 	/* IRQ3 */
2006 	RCAR_GP_PIN(1, 27),
2007 };
2008 static const unsigned int intc_ex_irq3_mux[] = {
2009 	IRQ3_MARK,
2010 };
2011 static const unsigned int intc_ex_irq4_pins[] = {
2012 	/* IRQ4 */
2013 	RCAR_GP_PIN(2, 14),
2014 };
2015 static const unsigned int intc_ex_irq4_mux[] = {
2016 	IRQ4_MARK,
2017 };
2018 static const unsigned int intc_ex_irq5_pins[] = {
2019 	/* IRQ5 */
2020 	RCAR_GP_PIN(2, 15),
2021 };
2022 static const unsigned int intc_ex_irq5_mux[] = {
2023 	IRQ5_MARK,
2024 };
2025 
2026 /* - MMC -------------------------------------------------------------------- */
2027 static const unsigned int mmc_data_pins[] = {
2028 	/* MMC_SD_D[0:3], MMC_D[4:7] */
2029 	RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
2030 	RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
2031 	RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2032 	RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27),
2033 };
2034 static const unsigned int mmc_data_mux[] = {
2035 	MMC_SD_D0_MARK, MMC_SD_D1_MARK,
2036 	MMC_SD_D2_MARK, MMC_SD_D3_MARK,
2037 	MMC_D4_MARK, MMC_D5_MARK,
2038 	MMC_D6_MARK, MMC_D7_MARK,
2039 };
2040 static const unsigned int mmc_ctrl_pins[] = {
2041 	/* MMC_SD_CLK, MMC_SD_CMD */
2042 	RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18),
2043 };
2044 static const unsigned int mmc_ctrl_mux[] = {
2045 	MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
2046 };
2047 static const unsigned int mmc_cd_pins[] = {
2048 	/* SD_CD */
2049 	RCAR_GP_PIN(0, 16),
2050 };
2051 static const unsigned int mmc_cd_mux[] = {
2052 	SD_CD_MARK,
2053 };
2054 static const unsigned int mmc_wp_pins[] = {
2055 	/* SD_WP */
2056 	RCAR_GP_PIN(0, 15),
2057 };
2058 static const unsigned int mmc_wp_mux[] = {
2059 	SD_WP_MARK,
2060 };
2061 static const unsigned int mmc_ds_pins[] = {
2062 	/* MMC_DS */
2063 	RCAR_GP_PIN(0, 17),
2064 };
2065 static const unsigned int mmc_ds_mux[] = {
2066 	MMC_DS_MARK,
2067 };
2068 
2069 /* - MSIOF0 ----------------------------------------------------------------- */
2070 static const unsigned int msiof0_clk_pins[] = {
2071 	/* MSIOF0_SCK */
2072 	RCAR_GP_PIN(1, 8),
2073 };
2074 static const unsigned int msiof0_clk_mux[] = {
2075 	MSIOF0_SCK_MARK,
2076 };
2077 static const unsigned int msiof0_sync_pins[] = {
2078 	/* MSIOF0_SYNC */
2079 	RCAR_GP_PIN(1, 9),
2080 };
2081 static const unsigned int msiof0_sync_mux[] = {
2082 	MSIOF0_SYNC_MARK,
2083 };
2084 static const unsigned int msiof0_ss1_pins[] = {
2085 	/* MSIOF0_SS1 */
2086 	RCAR_GP_PIN(1, 10),
2087 };
2088 static const unsigned int msiof0_ss1_mux[] = {
2089 	MSIOF0_SS1_MARK,
2090 };
2091 static const unsigned int msiof0_ss2_pins[] = {
2092 	/* MSIOF0_SS2 */
2093 	RCAR_GP_PIN(1, 11),
2094 };
2095 static const unsigned int msiof0_ss2_mux[] = {
2096 	MSIOF0_SS2_MARK,
2097 };
2098 static const unsigned int msiof0_txd_pins[] = {
2099 	/* MSIOF0_TXD */
2100 	RCAR_GP_PIN(1, 7),
2101 };
2102 static const unsigned int msiof0_txd_mux[] = {
2103 	MSIOF0_TXD_MARK,
2104 };
2105 static const unsigned int msiof0_rxd_pins[] = {
2106 	/* MSIOF0_RXD */
2107 	RCAR_GP_PIN(1, 6),
2108 };
2109 static const unsigned int msiof0_rxd_mux[] = {
2110 	MSIOF0_RXD_MARK,
2111 };
2112 
2113 /* - MSIOF1 ----------------------------------------------------------------- */
2114 static const unsigned int msiof1_clk_pins[] = {
2115 	/* MSIOF1_SCK */
2116 	RCAR_GP_PIN(1, 14),
2117 };
2118 static const unsigned int msiof1_clk_mux[] = {
2119 	MSIOF1_SCK_MARK,
2120 };
2121 static const unsigned int msiof1_sync_pins[] = {
2122 	/* MSIOF1_SYNC */
2123 	RCAR_GP_PIN(1, 15),
2124 };
2125 static const unsigned int msiof1_sync_mux[] = {
2126 	MSIOF1_SYNC_MARK,
2127 };
2128 static const unsigned int msiof1_ss1_pins[] = {
2129 	/* MSIOF1_SS1 */
2130 	RCAR_GP_PIN(1, 16),
2131 };
2132 static const unsigned int msiof1_ss1_mux[] = {
2133 	MSIOF1_SS1_MARK,
2134 };
2135 static const unsigned int msiof1_ss2_pins[] = {
2136 	/* MSIOF1_SS2 */
2137 	RCAR_GP_PIN(1, 17),
2138 };
2139 static const unsigned int msiof1_ss2_mux[] = {
2140 	MSIOF1_SS2_MARK,
2141 };
2142 static const unsigned int msiof1_txd_pins[] = {
2143 	/* MSIOF1_TXD */
2144 	RCAR_GP_PIN(1, 13),
2145 };
2146 static const unsigned int msiof1_txd_mux[] = {
2147 	MSIOF1_TXD_MARK,
2148 };
2149 static const unsigned int msiof1_rxd_pins[] = {
2150 	/* MSIOF1_RXD */
2151 	RCAR_GP_PIN(1, 12),
2152 };
2153 static const unsigned int msiof1_rxd_mux[] = {
2154 	MSIOF1_RXD_MARK,
2155 };
2156 
2157 /* - MSIOF2 ----------------------------------------------------------------- */
2158 static const unsigned int msiof2_clk_pins[] = {
2159 	/* MSIOF2_SCK */
2160 	RCAR_GP_PIN(1, 20),
2161 };
2162 static const unsigned int msiof2_clk_mux[] = {
2163 	MSIOF2_SCK_MARK,
2164 };
2165 static const unsigned int msiof2_sync_pins[] = {
2166 	/* MSIOF2_SYNC */
2167 	RCAR_GP_PIN(1, 21),
2168 };
2169 static const unsigned int msiof2_sync_mux[] = {
2170 	MSIOF2_SYNC_MARK,
2171 };
2172 static const unsigned int msiof2_ss1_pins[] = {
2173 	/* MSIOF2_SS1 */
2174 	RCAR_GP_PIN(1, 22),
2175 };
2176 static const unsigned int msiof2_ss1_mux[] = {
2177 	MSIOF2_SS1_MARK,
2178 };
2179 static const unsigned int msiof2_ss2_pins[] = {
2180 	/* MSIOF2_SS2 */
2181 	RCAR_GP_PIN(1, 23),
2182 };
2183 static const unsigned int msiof2_ss2_mux[] = {
2184 	MSIOF2_SS2_MARK,
2185 };
2186 static const unsigned int msiof2_txd_pins[] = {
2187 	/* MSIOF2_TXD */
2188 	RCAR_GP_PIN(1, 19),
2189 };
2190 static const unsigned int msiof2_txd_mux[] = {
2191 	MSIOF2_TXD_MARK,
2192 };
2193 static const unsigned int msiof2_rxd_pins[] = {
2194 	/* MSIOF2_RXD */
2195 	RCAR_GP_PIN(1, 18),
2196 };
2197 static const unsigned int msiof2_rxd_mux[] = {
2198 	MSIOF2_RXD_MARK,
2199 };
2200 
2201 /* - MSIOF3 ----------------------------------------------------------------- */
2202 static const unsigned int msiof3_clk_pins[] = {
2203 	/* MSIOF3_SCK */
2204 	RCAR_GP_PIN(2, 20),
2205 };
2206 static const unsigned int msiof3_clk_mux[] = {
2207 	MSIOF3_SCK_MARK,
2208 };
2209 static const unsigned int msiof3_sync_pins[] = {
2210 	/* MSIOF3_SYNC */
2211 	RCAR_GP_PIN(2, 21),
2212 };
2213 static const unsigned int msiof3_sync_mux[] = {
2214 	MSIOF3_SYNC_MARK,
2215 };
2216 static const unsigned int msiof3_ss1_pins[] = {
2217 	/* MSIOF3_SS1 */
2218 	RCAR_GP_PIN(2, 16),
2219 };
2220 static const unsigned int msiof3_ss1_mux[] = {
2221 	MSIOF3_SS1_MARK,
2222 };
2223 static const unsigned int msiof3_ss2_pins[] = {
2224 	/* MSIOF3_SS2 */
2225 	RCAR_GP_PIN(2, 17),
2226 };
2227 static const unsigned int msiof3_ss2_mux[] = {
2228 	MSIOF3_SS2_MARK,
2229 };
2230 static const unsigned int msiof3_txd_pins[] = {
2231 	/* MSIOF3_TXD */
2232 	RCAR_GP_PIN(2, 19),
2233 };
2234 static const unsigned int msiof3_txd_mux[] = {
2235 	MSIOF3_TXD_MARK,
2236 };
2237 static const unsigned int msiof3_rxd_pins[] = {
2238 	/* MSIOF3_RXD */
2239 	RCAR_GP_PIN(2, 18),
2240 };
2241 static const unsigned int msiof3_rxd_mux[] = {
2242 	MSIOF3_RXD_MARK,
2243 };
2244 
2245 /* - MSIOF4 ----------------------------------------------------------------- */
2246 static const unsigned int msiof4_clk_pins[] = {
2247 	/* MSIOF4_SCK */
2248 	RCAR_GP_PIN(2, 6),
2249 };
2250 static const unsigned int msiof4_clk_mux[] = {
2251 	MSIOF4_SCK_MARK,
2252 };
2253 static const unsigned int msiof4_sync_pins[] = {
2254 	/* MSIOF4_SYNC */
2255 	RCAR_GP_PIN(2, 7),
2256 };
2257 static const unsigned int msiof4_sync_mux[] = {
2258 	MSIOF4_SYNC_MARK,
2259 };
2260 static const unsigned int msiof4_ss1_pins[] = {
2261 	/* MSIOF4_SS1 */
2262 	RCAR_GP_PIN(2, 8),
2263 };
2264 static const unsigned int msiof4_ss1_mux[] = {
2265 	MSIOF4_SS1_MARK,
2266 };
2267 static const unsigned int msiof4_ss2_pins[] = {
2268 	/* MSIOF4_SS2 */
2269 	RCAR_GP_PIN(2, 9),
2270 };
2271 static const unsigned int msiof4_ss2_mux[] = {
2272 	MSIOF4_SS2_MARK,
2273 };
2274 static const unsigned int msiof4_txd_pins[] = {
2275 	/* MSIOF4_TXD */
2276 	RCAR_GP_PIN(2, 5),
2277 };
2278 static const unsigned int msiof4_txd_mux[] = {
2279 	MSIOF4_TXD_MARK,
2280 };
2281 static const unsigned int msiof4_rxd_pins[] = {
2282 	/* MSIOF4_RXD */
2283 	RCAR_GP_PIN(2, 4),
2284 };
2285 static const unsigned int msiof4_rxd_mux[] = {
2286 	MSIOF4_RXD_MARK,
2287 };
2288 
2289 /* - MSIOF5 ----------------------------------------------------------------- */
2290 static const unsigned int msiof5_clk_pins[] = {
2291 	/* MSIOF5_SCK */
2292 	RCAR_GP_PIN(2, 12),
2293 };
2294 static const unsigned int msiof5_clk_mux[] = {
2295 	MSIOF5_SCK_MARK,
2296 };
2297 static const unsigned int msiof5_sync_pins[] = {
2298 	/* MSIOF5_SYNC */
2299 	RCAR_GP_PIN(2, 13),
2300 };
2301 static const unsigned int msiof5_sync_mux[] = {
2302 	MSIOF5_SYNC_MARK,
2303 };
2304 static const unsigned int msiof5_ss1_pins[] = {
2305 	/* MSIOF5_SS1 */
2306 	RCAR_GP_PIN(2, 14),
2307 };
2308 static const unsigned int msiof5_ss1_mux[] = {
2309 	MSIOF5_SS1_MARK,
2310 };
2311 static const unsigned int msiof5_ss2_pins[] = {
2312 	/* MSIOF5_SS2 */
2313 	RCAR_GP_PIN(2, 15),
2314 };
2315 static const unsigned int msiof5_ss2_mux[] = {
2316 	MSIOF5_SS2_MARK,
2317 };
2318 static const unsigned int msiof5_txd_pins[] = {
2319 	/* MSIOF5_TXD */
2320 	RCAR_GP_PIN(2, 11),
2321 };
2322 static const unsigned int msiof5_txd_mux[] = {
2323 	MSIOF5_TXD_MARK,
2324 };
2325 static const unsigned int msiof5_rxd_pins[] = {
2326 	/* MSIOF5_RXD */
2327 	RCAR_GP_PIN(2, 10),
2328 };
2329 static const unsigned int msiof5_rxd_mux[] = {
2330 	MSIOF5_RXD_MARK,
2331 };
2332 
2333 /* - PWM0 ------------------------------------------------------------------- */
2334 static const unsigned int pwm0_pins[] = {
2335 	/* PWM0 */
2336 	RCAR_GP_PIN(3, 5),
2337 };
2338 static const unsigned int pwm0_mux[] = {
2339 	PWM0_MARK,
2340 };
2341 
2342 /* - PWM1 ------------------------------------------------------------------- */
2343 static const unsigned int pwm1_pins[] = {
2344 	/* PWM1 */
2345 	RCAR_GP_PIN(3, 6),
2346 };
2347 static const unsigned int pwm1_mux[] = {
2348 	PWM1_MARK,
2349 };
2350 
2351 /* - PWM2 ------------------------------------------------------------------- */
2352 static const unsigned int pwm2_pins[] = {
2353 	/* PWM2 */
2354 	RCAR_GP_PIN(3, 7),
2355 };
2356 static const unsigned int pwm2_mux[] = {
2357 	PWM2_MARK,
2358 };
2359 
2360 /* - PWM3 ------------------------------------------------------------------- */
2361 static const unsigned int pwm3_pins[] = {
2362 	/* PWM3 */
2363 	RCAR_GP_PIN(3, 8),
2364 };
2365 static const unsigned int pwm3_mux[] = {
2366 	PWM3_MARK,
2367 };
2368 
2369 /* - PWM4 ------------------------------------------------------------------- */
2370 static const unsigned int pwm4_pins[] = {
2371 	/* PWM4 */
2372 	RCAR_GP_PIN(3, 9),
2373 };
2374 static const unsigned int pwm4_mux[] = {
2375 	PWM4_MARK,
2376 };
2377 
2378 /* - QSPI0 ------------------------------------------------------------------ */
2379 static const unsigned int qspi0_ctrl_pins[] = {
2380 	/* SPCLK, SSL */
2381 	RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5),
2382 };
2383 static const unsigned int qspi0_ctrl_mux[] = {
2384 	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2385 };
2386 static const unsigned int qspi0_data_pins[] = {
2387 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2388 	RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2389 	RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2390 };
2391 static const unsigned int qspi0_data_mux[] = {
2392 	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2393 	QSPI0_IO2_MARK, QSPI0_IO3_MARK
2394 };
2395 
2396 /* - QSPI1 ------------------------------------------------------------------ */
2397 static const unsigned int qspi1_ctrl_pins[] = {
2398 	/* SPCLK, SSL */
2399 	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11),
2400 };
2401 static const unsigned int qspi1_ctrl_mux[] = {
2402 	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2403 };
2404 static const unsigned int qspi1_data_pins[] = {
2405 	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
2406 	RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
2407 	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2408 };
2409 static const unsigned int qspi1_data_mux[] = {
2410 	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2411 	QSPI1_IO2_MARK, QSPI1_IO3_MARK
2412 };
2413 
2414 /* - SCIF0 ------------------------------------------------------------------ */
2415 static const unsigned int scif0_data_pins[] = {
2416 	/* RX0, TX0 */
2417 	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
2418 };
2419 static const unsigned int scif0_data_mux[] = {
2420 	RX0_MARK, TX0_MARK,
2421 };
2422 static const unsigned int scif0_clk_pins[] = {
2423 	/* SCK0 */
2424 	RCAR_GP_PIN(1, 2),
2425 };
2426 static const unsigned int scif0_clk_mux[] = {
2427 	SCK0_MARK,
2428 };
2429 static const unsigned int scif0_ctrl_pins[] = {
2430 	/* RTS0#, CTS0# */
2431 	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
2432 };
2433 static const unsigned int scif0_ctrl_mux[] = {
2434 	RTS0_N_MARK, CTS0_N_MARK,
2435 };
2436 
2437 /* - SCIF1 ------------------------------------------------------------------ */
2438 static const unsigned int scif1_data_a_pins[] = {
2439 	/* RX, TX */
2440 	RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2441 };
2442 static const unsigned int scif1_data_a_mux[] = {
2443 	RX1_A_MARK, TX1_A_MARK,
2444 };
2445 static const unsigned int scif1_data_b_pins[] = {
2446 	/* RX, TX */
2447 	RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 1),
2448 };
2449 static const unsigned int scif1_data_b_mux[] = {
2450 	RX1_B_MARK, TX1_B_MARK,
2451 };
2452 static const unsigned int scif1_clk_pins[] = {
2453 	/* SCK1 */
2454 	RCAR_GP_PIN(1, 18),
2455 };
2456 static const unsigned int scif1_clk_mux[] = {
2457 	SCK1_MARK,
2458 };
2459 static const unsigned int scif1_ctrl_pins[] = {
2460 	/* RTS1#, CTS1# */
2461 	RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
2462 };
2463 static const unsigned int scif1_ctrl_mux[] = {
2464 	RTS1_N_MARK, CTS1_N_MARK,
2465 };
2466 
2467 /* - SCIF3 ------------------------------------------------------------------ */
2468 static const unsigned int scif3_data_pins[] = {
2469 	/* RX3, TX3 */
2470 	RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2471 };
2472 static const unsigned int scif3_data_mux[] = {
2473 	RX3_MARK, TX3_MARK,
2474 };
2475 static const unsigned int scif3_clk_pins[] = {
2476 	/* SCK3 */
2477 	RCAR_GP_PIN(1, 13),
2478 };
2479 static const unsigned int scif3_clk_mux[] = {
2480 	SCK3_MARK,
2481 };
2482 static const unsigned int scif3_ctrl_pins[] = {
2483 	/* RTS3#, CTS3# */
2484 	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2485 };
2486 static const unsigned int scif3_ctrl_mux[] = {
2487 	RTS3_N_MARK, CTS3_N_MARK,
2488 };
2489 
2490 /* - SCIF4 ------------------------------------------------------------------ */
2491 static const unsigned int scif4_data_pins[] = {
2492 	/* RX4, TX4 */
2493 	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2494 };
2495 static const unsigned int scif4_data_mux[] = {
2496 	RX4_MARK, TX4_MARK,
2497 };
2498 static const unsigned int scif4_clk_pins[] = {
2499 	/* SCK4 */
2500 	RCAR_GP_PIN(2, 5),
2501 };
2502 static const unsigned int scif4_clk_mux[] = {
2503 	SCK4_MARK,
2504 };
2505 static const unsigned int scif4_ctrl_pins[] = {
2506 	/* RTS4#, CTS4# */
2507 	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
2508 };
2509 static const unsigned int scif4_ctrl_mux[] = {
2510 	RTS4_N_MARK, CTS4_N_MARK,
2511 };
2512 
2513 /* - SCIF Clock ------------------------------------------------------------- */
2514 static const unsigned int scif_clk_pins[] = {
2515 	/* SCIF_CLK */
2516 	RCAR_GP_PIN(1, 0),
2517 };
2518 static const unsigned int scif_clk_mux[] = {
2519 	SCIF_CLK_MARK,
2520 };
2521 
2522 /* - TMU -------------------------------------------------------------------- */
2523 static const unsigned int tmu_tclk1_a_pins[] = {
2524 	/* TCLK1 */
2525 	RCAR_GP_PIN(2, 23),
2526 };
2527 static const unsigned int tmu_tclk1_a_mux[] = {
2528 	TCLK1_A_MARK,
2529 };
2530 static const unsigned int tmu_tclk1_b_pins[] = {
2531 	/* TCLK1 */
2532 	RCAR_GP_PIN(1, 23),
2533 };
2534 static const unsigned int tmu_tclk1_b_mux[] = {
2535 	TCLK1_B_MARK,
2536 };
2537 
2538 static const unsigned int tmu_tclk2_a_pins[] = {
2539 	/* TCLK2 */
2540 	RCAR_GP_PIN(2, 24),
2541 };
2542 static const unsigned int tmu_tclk2_a_mux[] = {
2543 	TCLK2_A_MARK,
2544 };
2545 static const unsigned int tmu_tclk2_b_pins[] = {
2546 	/* TCLK2 */
2547 	RCAR_GP_PIN(2, 10),
2548 };
2549 static const unsigned int tmu_tclk2_b_mux[] = {
2550 	TCLK2_B_MARK,
2551 };
2552 
2553 static const unsigned int tmu_tclk3_pins[] = {
2554 	/* TCLK3 */
2555 	RCAR_GP_PIN(2, 11),
2556 };
2557 static const unsigned int tmu_tclk3_mux[] = {
2558 	TCLK3_MARK,
2559 };
2560 
2561 static const unsigned int tmu_tclk4_pins[] = {
2562 	/* TCLK4 */
2563 	RCAR_GP_PIN(2, 12),
2564 };
2565 static const unsigned int tmu_tclk4_mux[] = {
2566 	TCLK4_MARK,
2567 };
2568 
2569 /* - TPU ------------------------------------------------------------------- */
2570 static const unsigned int tpu_to0_pins[] = {
2571 	/* TPU0TO0 */
2572 	RCAR_GP_PIN(2, 21),
2573 };
2574 static const unsigned int tpu_to0_mux[] = {
2575 	TPU0TO0_MARK,
2576 };
2577 static const unsigned int tpu_to1_pins[] = {
2578 	/* TPU0TO1 */
2579 	RCAR_GP_PIN(2, 22),
2580 };
2581 static const unsigned int tpu_to1_mux[] = {
2582 	TPU0TO1_MARK,
2583 };
2584 static const unsigned int tpu_to2_pins[] = {
2585 	/* TPU0TO2 */
2586 	RCAR_GP_PIN(3, 5),
2587 };
2588 static const unsigned int tpu_to2_mux[] = {
2589 	TPU0TO2_MARK,
2590 };
2591 static const unsigned int tpu_to3_pins[] = {
2592 	/* TPU0TO3 */
2593 	RCAR_GP_PIN(3, 6),
2594 };
2595 static const unsigned int tpu_to3_mux[] = {
2596 	TPU0TO3_MARK,
2597 };
2598 
2599 static const struct sh_pfc_pin_group pinmux_groups[] = {
2600 	SH_PFC_PIN_GROUP(avb0_link),
2601 	SH_PFC_PIN_GROUP(avb0_magic),
2602 	SH_PFC_PIN_GROUP(avb0_phy_int),
2603 	SH_PFC_PIN_GROUP(avb0_mdio),
2604 	SH_PFC_PIN_GROUP(avb0_rgmii),
2605 	SH_PFC_PIN_GROUP(avb0_txcrefclk),
2606 	SH_PFC_PIN_GROUP(avb0_avtp_pps),
2607 	SH_PFC_PIN_GROUP(avb0_avtp_capture),
2608 	SH_PFC_PIN_GROUP(avb0_avtp_match),
2609 
2610 	SH_PFC_PIN_GROUP(avb1_link),
2611 	SH_PFC_PIN_GROUP(avb1_magic),
2612 	SH_PFC_PIN_GROUP(avb1_phy_int),
2613 	SH_PFC_PIN_GROUP(avb1_mdio),
2614 	SH_PFC_PIN_GROUP(avb1_rgmii),
2615 	SH_PFC_PIN_GROUP(avb1_txcrefclk),
2616 	SH_PFC_PIN_GROUP(avb1_avtp_pps),
2617 	SH_PFC_PIN_GROUP(avb1_avtp_capture),
2618 	SH_PFC_PIN_GROUP(avb1_avtp_match),
2619 
2620 	SH_PFC_PIN_GROUP(avb2_link),
2621 	SH_PFC_PIN_GROUP(avb2_magic),
2622 	SH_PFC_PIN_GROUP(avb2_phy_int),
2623 	SH_PFC_PIN_GROUP(avb2_mdio),
2624 	SH_PFC_PIN_GROUP(avb2_rgmii),
2625 	SH_PFC_PIN_GROUP(avb2_txcrefclk),
2626 	SH_PFC_PIN_GROUP(avb2_avtp_pps),
2627 	SH_PFC_PIN_GROUP(avb2_avtp_capture),
2628 	SH_PFC_PIN_GROUP(avb2_avtp_match),
2629 
2630 	SH_PFC_PIN_GROUP(avb3_link),
2631 	SH_PFC_PIN_GROUP(avb3_magic),
2632 	SH_PFC_PIN_GROUP(avb3_phy_int),
2633 	SH_PFC_PIN_GROUP(avb3_mdio),
2634 	SH_PFC_PIN_GROUP(avb3_rgmii),
2635 	SH_PFC_PIN_GROUP(avb3_txcrefclk),
2636 	SH_PFC_PIN_GROUP(avb3_avtp_pps),
2637 	SH_PFC_PIN_GROUP(avb3_avtp_capture),
2638 	SH_PFC_PIN_GROUP(avb3_avtp_match),
2639 
2640 	SH_PFC_PIN_GROUP(avb4_link),
2641 	SH_PFC_PIN_GROUP(avb4_magic),
2642 	SH_PFC_PIN_GROUP(avb4_phy_int),
2643 	SH_PFC_PIN_GROUP(avb4_mdio),
2644 	SH_PFC_PIN_GROUP(avb4_rgmii),
2645 	SH_PFC_PIN_GROUP(avb4_txcrefclk),
2646 	SH_PFC_PIN_GROUP(avb4_avtp_pps),
2647 	SH_PFC_PIN_GROUP(avb4_avtp_capture),
2648 	SH_PFC_PIN_GROUP(avb4_avtp_match),
2649 
2650 	SH_PFC_PIN_GROUP(avb5_link),
2651 	SH_PFC_PIN_GROUP(avb5_magic),
2652 	SH_PFC_PIN_GROUP(avb5_phy_int),
2653 	SH_PFC_PIN_GROUP(avb5_mdio),
2654 	SH_PFC_PIN_GROUP(avb5_rgmii),
2655 	SH_PFC_PIN_GROUP(avb5_txcrefclk),
2656 	SH_PFC_PIN_GROUP(avb5_avtp_pps),
2657 	SH_PFC_PIN_GROUP(avb5_avtp_capture),
2658 	SH_PFC_PIN_GROUP(avb5_avtp_match),
2659 
2660 	SH_PFC_PIN_GROUP(canfd0_data),
2661 	SH_PFC_PIN_GROUP(canfd1_data),
2662 	SH_PFC_PIN_GROUP(canfd2_data),
2663 	SH_PFC_PIN_GROUP(canfd3_data),
2664 	SH_PFC_PIN_GROUP(canfd4_data),
2665 	SH_PFC_PIN_GROUP(canfd5_data),
2666 	SH_PFC_PIN_GROUP(canfd6_data),
2667 	SH_PFC_PIN_GROUP(canfd7_data),
2668 	SH_PFC_PIN_GROUP(can_clk),
2669 
2670 	SH_PFC_PIN_GROUP(du_rgb888),
2671 	SH_PFC_PIN_GROUP(du_clk_out),
2672 	SH_PFC_PIN_GROUP(du_sync),
2673 	SH_PFC_PIN_GROUP(du_oddf),
2674 
2675 	SH_PFC_PIN_GROUP(hscif0_data),
2676 	SH_PFC_PIN_GROUP(hscif0_clk),
2677 	SH_PFC_PIN_GROUP(hscif0_ctrl),
2678 	SH_PFC_PIN_GROUP(hscif1_data),
2679 	SH_PFC_PIN_GROUP(hscif1_clk),
2680 	SH_PFC_PIN_GROUP(hscif1_ctrl),
2681 	SH_PFC_PIN_GROUP(hscif2_data),
2682 	SH_PFC_PIN_GROUP(hscif2_clk),
2683 	SH_PFC_PIN_GROUP(hscif2_ctrl),
2684 	SH_PFC_PIN_GROUP(hscif3_data),
2685 	SH_PFC_PIN_GROUP(hscif3_clk),
2686 	SH_PFC_PIN_GROUP(hscif3_ctrl),
2687 
2688 	SH_PFC_PIN_GROUP(i2c0),
2689 	SH_PFC_PIN_GROUP(i2c1),
2690 	SH_PFC_PIN_GROUP(i2c2),
2691 	SH_PFC_PIN_GROUP(i2c3),
2692 	SH_PFC_PIN_GROUP(i2c4),
2693 	SH_PFC_PIN_GROUP(i2c5),
2694 	SH_PFC_PIN_GROUP(i2c6),
2695 
2696 	SH_PFC_PIN_GROUP(intc_ex_irq0),
2697 	SH_PFC_PIN_GROUP(intc_ex_irq1),
2698 	SH_PFC_PIN_GROUP(intc_ex_irq2),
2699 	SH_PFC_PIN_GROUP(intc_ex_irq3),
2700 	SH_PFC_PIN_GROUP(intc_ex_irq4),
2701 	SH_PFC_PIN_GROUP(intc_ex_irq5),
2702 
2703 	BUS_DATA_PIN_GROUP(mmc_data, 1),
2704 	BUS_DATA_PIN_GROUP(mmc_data, 4),
2705 	BUS_DATA_PIN_GROUP(mmc_data, 8),
2706 	SH_PFC_PIN_GROUP(mmc_ctrl),
2707 	SH_PFC_PIN_GROUP(mmc_cd),
2708 	SH_PFC_PIN_GROUP(mmc_wp),
2709 	SH_PFC_PIN_GROUP(mmc_ds),
2710 
2711 	SH_PFC_PIN_GROUP(msiof0_clk),
2712 	SH_PFC_PIN_GROUP(msiof0_sync),
2713 	SH_PFC_PIN_GROUP(msiof0_ss1),
2714 	SH_PFC_PIN_GROUP(msiof0_ss2),
2715 	SH_PFC_PIN_GROUP(msiof0_txd),
2716 	SH_PFC_PIN_GROUP(msiof0_rxd),
2717 	SH_PFC_PIN_GROUP(msiof1_clk),
2718 	SH_PFC_PIN_GROUP(msiof1_sync),
2719 	SH_PFC_PIN_GROUP(msiof1_ss1),
2720 	SH_PFC_PIN_GROUP(msiof1_ss2),
2721 	SH_PFC_PIN_GROUP(msiof1_txd),
2722 	SH_PFC_PIN_GROUP(msiof1_rxd),
2723 	SH_PFC_PIN_GROUP(msiof2_clk),
2724 	SH_PFC_PIN_GROUP(msiof2_sync),
2725 	SH_PFC_PIN_GROUP(msiof2_ss1),
2726 	SH_PFC_PIN_GROUP(msiof2_ss2),
2727 	SH_PFC_PIN_GROUP(msiof2_txd),
2728 	SH_PFC_PIN_GROUP(msiof2_rxd),
2729 	SH_PFC_PIN_GROUP(msiof3_clk),
2730 	SH_PFC_PIN_GROUP(msiof3_sync),
2731 	SH_PFC_PIN_GROUP(msiof3_ss1),
2732 	SH_PFC_PIN_GROUP(msiof3_ss2),
2733 	SH_PFC_PIN_GROUP(msiof3_txd),
2734 	SH_PFC_PIN_GROUP(msiof3_rxd),
2735 	SH_PFC_PIN_GROUP(msiof4_clk),
2736 	SH_PFC_PIN_GROUP(msiof4_sync),
2737 	SH_PFC_PIN_GROUP(msiof4_ss1),
2738 	SH_PFC_PIN_GROUP(msiof4_ss2),
2739 	SH_PFC_PIN_GROUP(msiof4_txd),
2740 	SH_PFC_PIN_GROUP(msiof4_rxd),
2741 	SH_PFC_PIN_GROUP(msiof5_clk),
2742 	SH_PFC_PIN_GROUP(msiof5_sync),
2743 	SH_PFC_PIN_GROUP(msiof5_ss1),
2744 	SH_PFC_PIN_GROUP(msiof5_ss2),
2745 	SH_PFC_PIN_GROUP(msiof5_txd),
2746 	SH_PFC_PIN_GROUP(msiof5_rxd),
2747 
2748 	SH_PFC_PIN_GROUP(pwm0),
2749 	SH_PFC_PIN_GROUP(pwm1),
2750 	SH_PFC_PIN_GROUP(pwm2),
2751 	SH_PFC_PIN_GROUP(pwm3),
2752 	SH_PFC_PIN_GROUP(pwm4),
2753 
2754 	SH_PFC_PIN_GROUP(qspi0_ctrl),
2755 	BUS_DATA_PIN_GROUP(qspi0_data, 2),
2756 	BUS_DATA_PIN_GROUP(qspi0_data, 4),
2757 	SH_PFC_PIN_GROUP(qspi1_ctrl),
2758 	BUS_DATA_PIN_GROUP(qspi1_data, 2),
2759 	BUS_DATA_PIN_GROUP(qspi1_data, 4),
2760 
2761 	SH_PFC_PIN_GROUP(scif0_data),
2762 	SH_PFC_PIN_GROUP(scif0_clk),
2763 	SH_PFC_PIN_GROUP(scif0_ctrl),
2764 	SH_PFC_PIN_GROUP(scif1_data_a),
2765 	SH_PFC_PIN_GROUP(scif1_data_b),
2766 	SH_PFC_PIN_GROUP(scif1_clk),
2767 	SH_PFC_PIN_GROUP(scif1_ctrl),
2768 	SH_PFC_PIN_GROUP(scif3_data),
2769 	SH_PFC_PIN_GROUP(scif3_clk),
2770 	SH_PFC_PIN_GROUP(scif3_ctrl),
2771 	SH_PFC_PIN_GROUP(scif4_data),
2772 	SH_PFC_PIN_GROUP(scif4_clk),
2773 	SH_PFC_PIN_GROUP(scif4_ctrl),
2774 	SH_PFC_PIN_GROUP(scif_clk),
2775 
2776 	SH_PFC_PIN_GROUP(tmu_tclk1_a),
2777 	SH_PFC_PIN_GROUP(tmu_tclk1_b),
2778 	SH_PFC_PIN_GROUP(tmu_tclk2_a),
2779 	SH_PFC_PIN_GROUP(tmu_tclk2_b),
2780 	SH_PFC_PIN_GROUP(tmu_tclk3),
2781 	SH_PFC_PIN_GROUP(tmu_tclk4),
2782 
2783 	SH_PFC_PIN_GROUP(tpu_to0),
2784 	SH_PFC_PIN_GROUP(tpu_to1),
2785 	SH_PFC_PIN_GROUP(tpu_to2),
2786 	SH_PFC_PIN_GROUP(tpu_to3),
2787 };
2788 
2789 static const char * const avb0_groups[] = {
2790 	"avb0_link",
2791 	"avb0_magic",
2792 	"avb0_phy_int",
2793 	"avb0_mdio",
2794 	"avb0_rgmii",
2795 	"avb0_txcrefclk",
2796 	"avb0_avtp_pps",
2797 	"avb0_avtp_capture",
2798 	"avb0_avtp_match",
2799 };
2800 
2801 static const char * const avb1_groups[] = {
2802 	"avb1_link",
2803 	"avb1_magic",
2804 	"avb1_phy_int",
2805 	"avb1_mdio",
2806 	"avb1_rgmii",
2807 	"avb1_txcrefclk",
2808 	"avb1_avtp_pps",
2809 	"avb1_avtp_capture",
2810 	"avb1_avtp_match",
2811 };
2812 
2813 static const char * const avb2_groups[] = {
2814 	"avb2_link",
2815 	"avb2_magic",
2816 	"avb2_phy_int",
2817 	"avb2_mdio",
2818 	"avb2_rgmii",
2819 	"avb2_txcrefclk",
2820 	"avb2_avtp_pps",
2821 	"avb2_avtp_capture",
2822 	"avb2_avtp_match",
2823 };
2824 
2825 static const char * const avb3_groups[] = {
2826 	"avb3_link",
2827 	"avb3_magic",
2828 	"avb3_phy_int",
2829 	"avb3_mdio",
2830 	"avb3_rgmii",
2831 	"avb3_txcrefclk",
2832 	"avb3_avtp_pps",
2833 	"avb3_avtp_capture",
2834 	"avb3_avtp_match",
2835 };
2836 
2837 static const char * const avb4_groups[] = {
2838 	"avb4_link",
2839 	"avb4_magic",
2840 	"avb4_phy_int",
2841 	"avb4_mdio",
2842 	"avb4_rgmii",
2843 	"avb4_txcrefclk",
2844 	"avb4_avtp_pps",
2845 	"avb4_avtp_capture",
2846 	"avb4_avtp_match",
2847 };
2848 
2849 static const char * const avb5_groups[] = {
2850 	"avb5_link",
2851 	"avb5_magic",
2852 	"avb5_phy_int",
2853 	"avb5_mdio",
2854 	"avb5_rgmii",
2855 	"avb5_txcrefclk",
2856 	"avb5_avtp_pps",
2857 	"avb5_avtp_capture",
2858 	"avb5_avtp_match",
2859 };
2860 
2861 static const char * const canfd0_groups[] = {
2862 	"canfd0_data",
2863 };
2864 
2865 static const char * const canfd1_groups[] = {
2866 	"canfd1_data",
2867 };
2868 
2869 static const char * const canfd2_groups[] = {
2870 	"canfd2_data",
2871 };
2872 
2873 static const char * const canfd3_groups[] = {
2874 	"canfd3_data",
2875 };
2876 
2877 static const char * const canfd4_groups[] = {
2878 	"canfd4_data",
2879 };
2880 
2881 static const char * const canfd5_groups[] = {
2882 	"canfd5_data",
2883 };
2884 
2885 static const char * const canfd6_groups[] = {
2886 	"canfd6_data",
2887 };
2888 
2889 static const char * const canfd7_groups[] = {
2890 	"canfd7_data",
2891 };
2892 
2893 static const char * const can_clk_groups[] = {
2894 	"can_clk",
2895 };
2896 
2897 static const char * const du_groups[] = {
2898 	"du_rgb888",
2899 	"du_clk_out",
2900 	"du_sync",
2901 	"du_oddf",
2902 };
2903 
2904 static const char * const hscif0_groups[] = {
2905 	"hscif0_data",
2906 	"hscif0_clk",
2907 	"hscif0_ctrl",
2908 };
2909 
2910 static const char * const hscif1_groups[] = {
2911 	"hscif1_data",
2912 	"hscif1_clk",
2913 	"hscif1_ctrl",
2914 };
2915 
2916 static const char * const hscif2_groups[] = {
2917 	"hscif2_data",
2918 	"hscif2_clk",
2919 	"hscif2_ctrl",
2920 };
2921 
2922 static const char * const hscif3_groups[] = {
2923 	"hscif3_data",
2924 	"hscif3_clk",
2925 	"hscif3_ctrl",
2926 };
2927 
2928 static const char * const i2c0_groups[] = {
2929 	"i2c0",
2930 };
2931 
2932 static const char * const i2c1_groups[] = {
2933 	"i2c1",
2934 };
2935 
2936 static const char * const i2c2_groups[] = {
2937 	"i2c2",
2938 };
2939 
2940 static const char * const i2c3_groups[] = {
2941 	"i2c3",
2942 };
2943 
2944 static const char * const i2c4_groups[] = {
2945 	"i2c4",
2946 };
2947 
2948 static const char * const i2c5_groups[] = {
2949 	"i2c5",
2950 };
2951 
2952 static const char * const i2c6_groups[] = {
2953 	"i2c6",
2954 };
2955 
2956 static const char * const intc_ex_groups[] = {
2957 	"intc_ex_irq0",
2958 	"intc_ex_irq1",
2959 	"intc_ex_irq2",
2960 	"intc_ex_irq3",
2961 	"intc_ex_irq4",
2962 	"intc_ex_irq5",
2963 };
2964 
2965 static const char * const mmc_groups[] = {
2966 	"mmc_data1",
2967 	"mmc_data4",
2968 	"mmc_data8",
2969 	"mmc_ctrl",
2970 	"mmc_cd",
2971 	"mmc_wp",
2972 	"mmc_ds",
2973 };
2974 
2975 static const char * const msiof0_groups[] = {
2976 	"msiof0_clk",
2977 	"msiof0_sync",
2978 	"msiof0_ss1",
2979 	"msiof0_ss2",
2980 	"msiof0_txd",
2981 	"msiof0_rxd",
2982 };
2983 
2984 static const char * const msiof1_groups[] = {
2985 	"msiof1_clk",
2986 	"msiof1_sync",
2987 	"msiof1_ss1",
2988 	"msiof1_ss2",
2989 	"msiof1_txd",
2990 	"msiof1_rxd",
2991 };
2992 
2993 static const char * const msiof2_groups[] = {
2994 	"msiof2_clk",
2995 	"msiof2_sync",
2996 	"msiof2_ss1",
2997 	"msiof2_ss2",
2998 	"msiof2_txd",
2999 	"msiof2_rxd",
3000 };
3001 
3002 static const char * const msiof3_groups[] = {
3003 	"msiof3_clk",
3004 	"msiof3_sync",
3005 	"msiof3_ss1",
3006 	"msiof3_ss2",
3007 	"msiof3_txd",
3008 	"msiof3_rxd",
3009 };
3010 
3011 static const char * const msiof4_groups[] = {
3012 	"msiof4_clk",
3013 	"msiof4_sync",
3014 	"msiof4_ss1",
3015 	"msiof4_ss2",
3016 	"msiof4_txd",
3017 	"msiof4_rxd",
3018 };
3019 
3020 static const char * const msiof5_groups[] = {
3021 	"msiof5_clk",
3022 	"msiof5_sync",
3023 	"msiof5_ss1",
3024 	"msiof5_ss2",
3025 	"msiof5_txd",
3026 	"msiof5_rxd",
3027 };
3028 
3029 static const char * const pwm0_groups[] = {
3030 	"pwm0",
3031 };
3032 
3033 static const char * const pwm1_groups[] = {
3034 	"pwm1",
3035 };
3036 
3037 static const char * const pwm2_groups[] = {
3038 	"pwm2",
3039 };
3040 
3041 static const char * const pwm3_groups[] = {
3042 	"pwm3",
3043 };
3044 
3045 static const char * const pwm4_groups[] = {
3046 	"pwm4",
3047 };
3048 
3049 static const char * const qspi0_groups[] = {
3050 	"qspi0_ctrl",
3051 	"qspi0_data2",
3052 	"qspi0_data4",
3053 };
3054 
3055 static const char * const qspi1_groups[] = {
3056 	"qspi1_ctrl",
3057 	"qspi1_data2",
3058 	"qspi1_data4",
3059 };
3060 
3061 static const char * const scif0_groups[] = {
3062 	"scif0_data",
3063 	"scif0_clk",
3064 	"scif0_ctrl",
3065 };
3066 
3067 static const char * const scif1_groups[] = {
3068 	"scif1_data_a",
3069 	"scif1_data_b",
3070 	"scif1_clk",
3071 	"scif1_ctrl",
3072 };
3073 
3074 static const char * const scif3_groups[] = {
3075 	"scif3_data",
3076 	"scif3_clk",
3077 	"scif3_ctrl",
3078 };
3079 
3080 static const char * const scif4_groups[] = {
3081 	"scif4_data",
3082 	"scif4_clk",
3083 	"scif4_ctrl",
3084 };
3085 
3086 static const char * const scif_clk_groups[] = {
3087 	"scif_clk",
3088 };
3089 
3090 static const char * const tmu_groups[] = {
3091 	"tmu_tclk1_a",
3092 	"tmu_tclk1_b",
3093 	"tmu_tclk2_a",
3094 	"tmu_tclk2_b",
3095 	"tmu_tclk3",
3096 	"tmu_tclk4",
3097 };
3098 
3099 static const char * const tpu_groups[] = {
3100 	"tpu_to0",
3101 	"tpu_to1",
3102 	"tpu_to2",
3103 	"tpu_to3",
3104 };
3105 
3106 static const struct sh_pfc_function pinmux_functions[] = {
3107 	SH_PFC_FUNCTION(avb0),
3108 	SH_PFC_FUNCTION(avb1),
3109 	SH_PFC_FUNCTION(avb2),
3110 	SH_PFC_FUNCTION(avb3),
3111 	SH_PFC_FUNCTION(avb4),
3112 	SH_PFC_FUNCTION(avb5),
3113 
3114 	SH_PFC_FUNCTION(canfd0),
3115 	SH_PFC_FUNCTION(canfd1),
3116 	SH_PFC_FUNCTION(canfd2),
3117 	SH_PFC_FUNCTION(canfd3),
3118 	SH_PFC_FUNCTION(canfd4),
3119 	SH_PFC_FUNCTION(canfd5),
3120 	SH_PFC_FUNCTION(canfd6),
3121 	SH_PFC_FUNCTION(canfd7),
3122 	SH_PFC_FUNCTION(can_clk),
3123 
3124 	SH_PFC_FUNCTION(du),
3125 
3126 	SH_PFC_FUNCTION(hscif0),
3127 	SH_PFC_FUNCTION(hscif1),
3128 	SH_PFC_FUNCTION(hscif2),
3129 	SH_PFC_FUNCTION(hscif3),
3130 
3131 	SH_PFC_FUNCTION(i2c0),
3132 	SH_PFC_FUNCTION(i2c1),
3133 	SH_PFC_FUNCTION(i2c2),
3134 	SH_PFC_FUNCTION(i2c3),
3135 	SH_PFC_FUNCTION(i2c4),
3136 	SH_PFC_FUNCTION(i2c5),
3137 	SH_PFC_FUNCTION(i2c6),
3138 
3139 	SH_PFC_FUNCTION(intc_ex),
3140 
3141 	SH_PFC_FUNCTION(mmc),
3142 
3143 	SH_PFC_FUNCTION(msiof0),
3144 	SH_PFC_FUNCTION(msiof1),
3145 	SH_PFC_FUNCTION(msiof2),
3146 	SH_PFC_FUNCTION(msiof3),
3147 	SH_PFC_FUNCTION(msiof4),
3148 	SH_PFC_FUNCTION(msiof5),
3149 
3150 	SH_PFC_FUNCTION(pwm0),
3151 	SH_PFC_FUNCTION(pwm1),
3152 	SH_PFC_FUNCTION(pwm2),
3153 	SH_PFC_FUNCTION(pwm3),
3154 	SH_PFC_FUNCTION(pwm4),
3155 
3156 	SH_PFC_FUNCTION(qspi0),
3157 	SH_PFC_FUNCTION(qspi1),
3158 
3159 	SH_PFC_FUNCTION(scif0),
3160 	SH_PFC_FUNCTION(scif1),
3161 	SH_PFC_FUNCTION(scif3),
3162 	SH_PFC_FUNCTION(scif4),
3163 	SH_PFC_FUNCTION(scif_clk),
3164 
3165 	SH_PFC_FUNCTION(tmu),
3166 
3167 	SH_PFC_FUNCTION(tpu),
3168 };
3169 
3170 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3171 #define F_(x, y)	FN_##y
3172 #define FM(x)		FN_##x
3173 	{ PINMUX_CFG_REG("GPSR0", 0xe6058040, 32, 1, GROUP(
3174 		0, 0,
3175 		0, 0,
3176 		0, 0,
3177 		0, 0,
3178 		GP_0_27_FN,	GPSR0_27,
3179 		GP_0_26_FN,	GPSR0_26,
3180 		GP_0_25_FN,	GPSR0_25,
3181 		GP_0_24_FN,	GPSR0_24,
3182 		GP_0_23_FN,	GPSR0_23,
3183 		GP_0_22_FN,	GPSR0_22,
3184 		GP_0_21_FN,	GPSR0_21,
3185 		GP_0_20_FN,	GPSR0_20,
3186 		GP_0_19_FN,	GPSR0_19,
3187 		GP_0_18_FN,	GPSR0_18,
3188 		GP_0_17_FN,	GPSR0_17,
3189 		GP_0_16_FN,	GPSR0_16,
3190 		GP_0_15_FN,	GPSR0_15,
3191 		GP_0_14_FN,	GPSR0_14,
3192 		GP_0_13_FN,	GPSR0_13,
3193 		GP_0_12_FN,	GPSR0_12,
3194 		GP_0_11_FN,	GPSR0_11,
3195 		GP_0_10_FN,	GPSR0_10,
3196 		GP_0_9_FN,	GPSR0_9,
3197 		GP_0_8_FN,	GPSR0_8,
3198 		GP_0_7_FN,	GPSR0_7,
3199 		GP_0_6_FN,	GPSR0_6,
3200 		GP_0_5_FN,	GPSR0_5,
3201 		GP_0_4_FN,	GPSR0_4,
3202 		GP_0_3_FN,	GPSR0_3,
3203 		GP_0_2_FN,	GPSR0_2,
3204 		GP_0_1_FN,	GPSR0_1,
3205 		GP_0_0_FN,	GPSR0_0, ))
3206 	},
3207 	{ PINMUX_CFG_REG("GPSR1", 0xe6050040, 32, 1, GROUP(
3208 		0, 0,
3209 		GP_1_30_FN,	GPSR1_30,
3210 		GP_1_29_FN,	GPSR1_29,
3211 		GP_1_28_FN,	GPSR1_28,
3212 		GP_1_27_FN,	GPSR1_27,
3213 		GP_1_26_FN,	GPSR1_26,
3214 		GP_1_25_FN,	GPSR1_25,
3215 		GP_1_24_FN,	GPSR1_24,
3216 		GP_1_23_FN,	GPSR1_23,
3217 		GP_1_22_FN,	GPSR1_22,
3218 		GP_1_21_FN,	GPSR1_21,
3219 		GP_1_20_FN,	GPSR1_20,
3220 		GP_1_19_FN,	GPSR1_19,
3221 		GP_1_18_FN,	GPSR1_18,
3222 		GP_1_17_FN,	GPSR1_17,
3223 		GP_1_16_FN,	GPSR1_16,
3224 		GP_1_15_FN,	GPSR1_15,
3225 		GP_1_14_FN,	GPSR1_14,
3226 		GP_1_13_FN,	GPSR1_13,
3227 		GP_1_12_FN,	GPSR1_12,
3228 		GP_1_11_FN,	GPSR1_11,
3229 		GP_1_10_FN,	GPSR1_10,
3230 		GP_1_9_FN,	GPSR1_9,
3231 		GP_1_8_FN,	GPSR1_8,
3232 		GP_1_7_FN,	GPSR1_7,
3233 		GP_1_6_FN,	GPSR1_6,
3234 		GP_1_5_FN,	GPSR1_5,
3235 		GP_1_4_FN,	GPSR1_4,
3236 		GP_1_3_FN,	GPSR1_3,
3237 		GP_1_2_FN,	GPSR1_2,
3238 		GP_1_1_FN,	GPSR1_1,
3239 		GP_1_0_FN,	GPSR1_0, ))
3240 	},
3241 	{ PINMUX_CFG_REG_VAR("GPSR2", 0xe6050840, 32,
3242 			     GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3243 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3244 			     GROUP(
3245 		/* GP2_31_25 RESERVED */
3246 		GP_2_24_FN,	GPSR2_24,
3247 		GP_2_23_FN,	GPSR2_23,
3248 		GP_2_22_FN,	GPSR2_22,
3249 		GP_2_21_FN,	GPSR2_21,
3250 		GP_2_20_FN,	GPSR2_20,
3251 		GP_2_19_FN,	GPSR2_19,
3252 		GP_2_18_FN,	GPSR2_18,
3253 		GP_2_17_FN,	GPSR2_17,
3254 		GP_2_16_FN,	GPSR2_16,
3255 		GP_2_15_FN,	GPSR2_15,
3256 		GP_2_14_FN,	GPSR2_14,
3257 		GP_2_13_FN,	GPSR2_13,
3258 		GP_2_12_FN,	GPSR2_12,
3259 		GP_2_11_FN,	GPSR2_11,
3260 		GP_2_10_FN,	GPSR2_10,
3261 		GP_2_9_FN,	GPSR2_9,
3262 		GP_2_8_FN,	GPSR2_8,
3263 		GP_2_7_FN,	GPSR2_7,
3264 		GP_2_6_FN,	GPSR2_6,
3265 		GP_2_5_FN,	GPSR2_5,
3266 		GP_2_4_FN,	GPSR2_4,
3267 		GP_2_3_FN,	GPSR2_3,
3268 		GP_2_2_FN,	GPSR2_2,
3269 		GP_2_1_FN,	GPSR2_1,
3270 		GP_2_0_FN,	GPSR2_0, ))
3271 	},
3272 	{ PINMUX_CFG_REG_VAR("GPSR3", 0xe6058840, 32,
3273 			     GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3274 				   1, 1, 1, 1, 1, 1),
3275 			     GROUP(
3276 		/* GP3_31_17 RESERVED */
3277 		GP_3_16_FN,	GPSR3_16,
3278 		GP_3_15_FN,	GPSR3_15,
3279 		GP_3_14_FN,	GPSR3_14,
3280 		GP_3_13_FN,	GPSR3_13,
3281 		GP_3_12_FN,	GPSR3_12,
3282 		GP_3_11_FN,	GPSR3_11,
3283 		GP_3_10_FN,	GPSR3_10,
3284 		GP_3_9_FN,	GPSR3_9,
3285 		GP_3_8_FN,	GPSR3_8,
3286 		GP_3_7_FN,	GPSR3_7,
3287 		GP_3_6_FN,	GPSR3_6,
3288 		GP_3_5_FN,	GPSR3_5,
3289 		GP_3_4_FN,	GPSR3_4,
3290 		GP_3_3_FN,	GPSR3_3,
3291 		GP_3_2_FN,	GPSR3_2,
3292 		GP_3_1_FN,	GPSR3_1,
3293 		GP_3_0_FN,	GPSR3_0, ))
3294 	},
3295 	{ PINMUX_CFG_REG("GPSR4", 0xe6060040, 32, 1, GROUP(
3296 		0, 0,
3297 		0, 0,
3298 		0, 0,
3299 		0, 0,
3300 		0, 0,
3301 		GP_4_26_FN,	GPSR4_26,
3302 		GP_4_25_FN,	GPSR4_25,
3303 		GP_4_24_FN,	GPSR4_24,
3304 		GP_4_23_FN,	GPSR4_23,
3305 		GP_4_22_FN,	GPSR4_22,
3306 		GP_4_21_FN,	GPSR4_21,
3307 		GP_4_20_FN,	GPSR4_20,
3308 		GP_4_19_FN,	GPSR4_19,
3309 		GP_4_18_FN,	GPSR4_18,
3310 		GP_4_17_FN,	GPSR4_17,
3311 		GP_4_16_FN,	GPSR4_16,
3312 		GP_4_15_FN,	GPSR4_15,
3313 		GP_4_14_FN,	GPSR4_14,
3314 		GP_4_13_FN,	GPSR4_13,
3315 		GP_4_12_FN,	GPSR4_12,
3316 		GP_4_11_FN,	GPSR4_11,
3317 		GP_4_10_FN,	GPSR4_10,
3318 		GP_4_9_FN,	GPSR4_9,
3319 		GP_4_8_FN,	GPSR4_8,
3320 		GP_4_7_FN,	GPSR4_7,
3321 		GP_4_6_FN,	GPSR4_6,
3322 		GP_4_5_FN,	GPSR4_5,
3323 		GP_4_4_FN,	GPSR4_4,
3324 		GP_4_3_FN,	GPSR4_3,
3325 		GP_4_2_FN,	GPSR4_2,
3326 		GP_4_1_FN,	GPSR4_1,
3327 		GP_4_0_FN,	GPSR4_0, ))
3328 	},
3329 	{ PINMUX_CFG_REG_VAR("GPSR5", 0xe6060840, 32,
3330 			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3331 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3332 			     GROUP(
3333 		/* GP5_31_21 RESERVED */
3334 		GP_5_20_FN,	GPSR5_20,
3335 		GP_5_19_FN,	GPSR5_19,
3336 		GP_5_18_FN,	GPSR5_18,
3337 		GP_5_17_FN,	GPSR5_17,
3338 		GP_5_16_FN,	GPSR5_16,
3339 		GP_5_15_FN,	GPSR5_15,
3340 		GP_5_14_FN,	GPSR5_14,
3341 		GP_5_13_FN,	GPSR5_13,
3342 		GP_5_12_FN,	GPSR5_12,
3343 		GP_5_11_FN,	GPSR5_11,
3344 		GP_5_10_FN,	GPSR5_10,
3345 		GP_5_9_FN,	GPSR5_9,
3346 		GP_5_8_FN,	GPSR5_8,
3347 		GP_5_7_FN,	GPSR5_7,
3348 		GP_5_6_FN,	GPSR5_6,
3349 		GP_5_5_FN,	GPSR5_5,
3350 		GP_5_4_FN,	GPSR5_4,
3351 		GP_5_3_FN,	GPSR5_3,
3352 		GP_5_2_FN,	GPSR5_2,
3353 		GP_5_1_FN,	GPSR5_1,
3354 		GP_5_0_FN,	GPSR5_0, ))
3355 	},
3356 	{ PINMUX_CFG_REG_VAR("GPSR6", 0xe6068040, 32,
3357 			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3358 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3359 			     GROUP(
3360 		/* GP6_31_21 RESERVED */
3361 		GP_6_20_FN,	GPSR6_20,
3362 		GP_6_19_FN,	GPSR6_19,
3363 		GP_6_18_FN,	GPSR6_18,
3364 		GP_6_17_FN,	GPSR6_17,
3365 		GP_6_16_FN,	GPSR6_16,
3366 		GP_6_15_FN,	GPSR6_15,
3367 		GP_6_14_FN,	GPSR6_14,
3368 		GP_6_13_FN,	GPSR6_13,
3369 		GP_6_12_FN,	GPSR6_12,
3370 		GP_6_11_FN,	GPSR6_11,
3371 		GP_6_10_FN,	GPSR6_10,
3372 		GP_6_9_FN,	GPSR6_9,
3373 		GP_6_8_FN,	GPSR6_8,
3374 		GP_6_7_FN,	GPSR6_7,
3375 		GP_6_6_FN,	GPSR6_6,
3376 		GP_6_5_FN,	GPSR6_5,
3377 		GP_6_4_FN,	GPSR6_4,
3378 		GP_6_3_FN,	GPSR6_3,
3379 		GP_6_2_FN,	GPSR6_2,
3380 		GP_6_1_FN,	GPSR6_1,
3381 		GP_6_0_FN,	GPSR6_0, ))
3382 	},
3383 	{ PINMUX_CFG_REG_VAR("GPSR7", 0xe6068840, 32,
3384 			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3385 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3386 			     GROUP(
3387 		/* GP7_31_21 RESERVED */
3388 		GP_7_20_FN,	GPSR7_20,
3389 		GP_7_19_FN,	GPSR7_19,
3390 		GP_7_18_FN,	GPSR7_18,
3391 		GP_7_17_FN,	GPSR7_17,
3392 		GP_7_16_FN,	GPSR7_16,
3393 		GP_7_15_FN,	GPSR7_15,
3394 		GP_7_14_FN,	GPSR7_14,
3395 		GP_7_13_FN,	GPSR7_13,
3396 		GP_7_12_FN,	GPSR7_12,
3397 		GP_7_11_FN,	GPSR7_11,
3398 		GP_7_10_FN,	GPSR7_10,
3399 		GP_7_9_FN,	GPSR7_9,
3400 		GP_7_8_FN,	GPSR7_8,
3401 		GP_7_7_FN,	GPSR7_7,
3402 		GP_7_6_FN,	GPSR7_6,
3403 		GP_7_5_FN,	GPSR7_5,
3404 		GP_7_4_FN,	GPSR7_4,
3405 		GP_7_3_FN,	GPSR7_3,
3406 		GP_7_2_FN,	GPSR7_2,
3407 		GP_7_1_FN,	GPSR7_1,
3408 		GP_7_0_FN,	GPSR7_0, ))
3409 	},
3410 	{ PINMUX_CFG_REG_VAR("GPSR8", 0xe6069040, 32,
3411 			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3412 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3413 			     GROUP(
3414 		/* GP8_31_21 RESERVED */
3415 		GP_8_20_FN,	GPSR8_20,
3416 		GP_8_19_FN,	GPSR8_19,
3417 		GP_8_18_FN,	GPSR8_18,
3418 		GP_8_17_FN,	GPSR8_17,
3419 		GP_8_16_FN,	GPSR8_16,
3420 		GP_8_15_FN,	GPSR8_15,
3421 		GP_8_14_FN,	GPSR8_14,
3422 		GP_8_13_FN,	GPSR8_13,
3423 		GP_8_12_FN,	GPSR8_12,
3424 		GP_8_11_FN,	GPSR8_11,
3425 		GP_8_10_FN,	GPSR8_10,
3426 		GP_8_9_FN,	GPSR8_9,
3427 		GP_8_8_FN,	GPSR8_8,
3428 		GP_8_7_FN,	GPSR8_7,
3429 		GP_8_6_FN,	GPSR8_6,
3430 		GP_8_5_FN,	GPSR8_5,
3431 		GP_8_4_FN,	GPSR8_4,
3432 		GP_8_3_FN,	GPSR8_3,
3433 		GP_8_2_FN,	GPSR8_2,
3434 		GP_8_1_FN,	GPSR8_1,
3435 		GP_8_0_FN,	GPSR8_0, ))
3436 	},
3437 	{ PINMUX_CFG_REG_VAR("GPSR9", 0xe6069840, 32,
3438 			     GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
3439 				   1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3440 			     GROUP(
3441 		/* GP9_31_21 RESERVED */
3442 		GP_9_20_FN,	GPSR9_20,
3443 		GP_9_19_FN,	GPSR9_19,
3444 		GP_9_18_FN,	GPSR9_18,
3445 		GP_9_17_FN,	GPSR9_17,
3446 		GP_9_16_FN,	GPSR9_16,
3447 		GP_9_15_FN,	GPSR9_15,
3448 		GP_9_14_FN,	GPSR9_14,
3449 		GP_9_13_FN,	GPSR9_13,
3450 		GP_9_12_FN,	GPSR9_12,
3451 		GP_9_11_FN,	GPSR9_11,
3452 		GP_9_10_FN,	GPSR9_10,
3453 		GP_9_9_FN,	GPSR9_9,
3454 		GP_9_8_FN,	GPSR9_8,
3455 		GP_9_7_FN,	GPSR9_7,
3456 		GP_9_6_FN,	GPSR9_6,
3457 		GP_9_5_FN,	GPSR9_5,
3458 		GP_9_4_FN,	GPSR9_4,
3459 		GP_9_3_FN,	GPSR9_3,
3460 		GP_9_2_FN,	GPSR9_2,
3461 		GP_9_1_FN,	GPSR9_1,
3462 		GP_9_0_FN,	GPSR9_0, ))
3463 	},
3464 #undef F_
3465 #undef FM
3466 
3467 #define F_(x, y)	x,
3468 #define FM(x)		FN_##x,
3469 	{ PINMUX_CFG_REG("IP0SR1", 0xe6050060, 32, 4, GROUP(
3470 		IP0SR1_31_28
3471 		IP0SR1_27_24
3472 		IP0SR1_23_20
3473 		IP0SR1_19_16
3474 		IP0SR1_15_12
3475 		IP0SR1_11_8
3476 		IP0SR1_7_4
3477 		IP0SR1_3_0))
3478 	},
3479 	{ PINMUX_CFG_REG("IP1SR1", 0xe6050064, 32, 4, GROUP(
3480 		IP1SR1_31_28
3481 		IP1SR1_27_24
3482 		IP1SR1_23_20
3483 		IP1SR1_19_16
3484 		IP1SR1_15_12
3485 		IP1SR1_11_8
3486 		IP1SR1_7_4
3487 		IP1SR1_3_0))
3488 	},
3489 	{ PINMUX_CFG_REG("IP2SR1", 0xe6050068, 32, 4, GROUP(
3490 		IP2SR1_31_28
3491 		IP2SR1_27_24
3492 		IP2SR1_23_20
3493 		IP2SR1_19_16
3494 		IP2SR1_15_12
3495 		IP2SR1_11_8
3496 		IP2SR1_7_4
3497 		IP2SR1_3_0))
3498 	},
3499 	{ PINMUX_CFG_REG_VAR("IP3SR1", 0xe605006c, 32,
3500 			      GROUP(-4, 4, 4, 4, 4, 4, 4, 4),
3501 			      GROUP(
3502 		/* IP3SR1_31_28 RESERVED */
3503 		IP3SR1_27_24
3504 		IP3SR1_23_20
3505 		IP3SR1_19_16
3506 		IP3SR1_15_12
3507 		IP3SR1_11_8
3508 		IP3SR1_7_4
3509 		IP3SR1_3_0))
3510 	},
3511 	{ PINMUX_CFG_REG("IP0SR2", 0xe6050860, 32, 4, GROUP(
3512 		IP0SR2_31_28
3513 		IP0SR2_27_24
3514 		IP0SR2_23_20
3515 		IP0SR2_19_16
3516 		IP0SR2_15_12
3517 		IP0SR2_11_8
3518 		IP0SR2_7_4
3519 		IP0SR2_3_0))
3520 	},
3521 	{ PINMUX_CFG_REG("IP1SR2", 0xe6050864, 32, 4, GROUP(
3522 		IP1SR2_31_28
3523 		IP1SR2_27_24
3524 		IP1SR2_23_20
3525 		IP1SR2_19_16
3526 		IP1SR2_15_12
3527 		IP1SR2_11_8
3528 		IP1SR2_7_4
3529 		IP1SR2_3_0))
3530 	},
3531 	{ PINMUX_CFG_REG("IP2SR2", 0xe6050868, 32, 4, GROUP(
3532 		IP2SR2_31_28
3533 		IP2SR2_27_24
3534 		IP2SR2_23_20
3535 		IP2SR2_19_16
3536 		IP2SR2_15_12
3537 		IP2SR2_11_8
3538 		IP2SR2_7_4
3539 		IP2SR2_3_0))
3540 	},
3541 	{ PINMUX_CFG_REG_VAR("IP0SR3", 0xe6058860, 32,
3542 			     GROUP(4, 4, 4, -8, 4, 4, -4),
3543 			     GROUP(
3544 		IP0SR3_31_28
3545 		IP0SR3_27_24
3546 		IP0SR3_23_20
3547 		/* IP0SR3_19_12 RESERVED */
3548 		IP0SR3_11_8
3549 		IP0SR3_7_4
3550 		/* IP0SR3_3_0 RESERVED */ ))
3551 	},
3552 	{ PINMUX_CFG_REG_VAR("IP1SR3", 0xe6058864, 32,
3553 			     GROUP(-8, 4, 4, 4, 4, 4, 4),
3554 			     GROUP(
3555 		/* IP1SR3_31_24 RESERVED */
3556 		IP1SR3_23_20
3557 		IP1SR3_19_16
3558 		IP1SR3_15_12
3559 		IP1SR3_11_8
3560 		IP1SR3_7_4
3561 		IP1SR3_3_0))
3562 	},
3563 	{ PINMUX_CFG_REG("IP0SR4", 0xe6060060, 32, 4, GROUP(
3564 		IP0SR4_31_28
3565 		IP0SR4_27_24
3566 		IP0SR4_23_20
3567 		IP0SR4_19_16
3568 		IP0SR4_15_12
3569 		IP0SR4_11_8
3570 		IP0SR4_7_4
3571 		IP0SR4_3_0))
3572 	},
3573 	{ PINMUX_CFG_REG("IP1SR4", 0xe6060064, 32, 4, GROUP(
3574 		IP1SR4_31_28
3575 		IP1SR4_27_24
3576 		IP1SR4_23_20
3577 		IP1SR4_19_16
3578 		IP1SR4_15_12
3579 		IP1SR4_11_8
3580 		IP1SR4_7_4
3581 		IP1SR4_3_0))
3582 	},
3583 	{ PINMUX_CFG_REG_VAR("IP2SR4", 0xe6060068, 32,
3584 			     GROUP(-12, 4, 4, 4, 4, -4),
3585 			     GROUP(
3586 		/* IP2SR4_31_20 RESERVED */
3587 		IP2SR4_19_16
3588 		IP2SR4_15_12
3589 		IP2SR4_11_8
3590 		IP2SR4_7_4
3591 		/* IP2SR4_3_0 RESERVED */ ))
3592 	},
3593 	{ PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP(
3594 		IP0SR5_31_28
3595 		IP0SR5_27_24
3596 		IP0SR5_23_20
3597 		IP0SR5_19_16
3598 		IP0SR5_15_12
3599 		IP0SR5_11_8
3600 		IP0SR5_7_4
3601 		IP0SR5_3_0))
3602 	},
3603 	{ PINMUX_CFG_REG("IP1SR5", 0xe6060864, 32, 4, GROUP(
3604 		IP1SR5_31_28
3605 		IP1SR5_27_24
3606 		IP1SR5_23_20
3607 		IP1SR5_19_16
3608 		IP1SR5_15_12
3609 		IP1SR5_11_8
3610 		IP1SR5_7_4
3611 		IP1SR5_3_0))
3612 	},
3613 	{ PINMUX_CFG_REG_VAR("IP2SR5", 0xe6060868, 32,
3614 			     GROUP(-12, 4, 4, 4, 4, -4),
3615 			     GROUP(
3616 		/* IP2SR5_31_20 RESERVED */
3617 		IP2SR5_19_16
3618 		IP2SR5_15_12
3619 		IP2SR5_11_8
3620 		IP2SR5_7_4
3621 		/* IP2SR5_3_0 RESERVED */ ))
3622 	},
3623 #undef F_
3624 #undef FM
3625 
3626 #define F_(x, y)	x,
3627 #define FM(x)		FN_##x,
3628 	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32,
3629 			     GROUP(-16, 2, 2, 2, 2, 2, 2, 2, -2),
3630 			     GROUP(
3631 		/* RESERVED 31-16 */
3632 		MOD_SEL2_15_14
3633 		MOD_SEL2_13_12
3634 		MOD_SEL2_11_10
3635 		MOD_SEL2_9_8
3636 		MOD_SEL2_7_6
3637 		MOD_SEL2_5_4
3638 		MOD_SEL2_3_2
3639 		/* RESERVED 1-0 */ ))
3640 	},
3641 	{ },
3642 };
3643 
3644 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
3645 	{ PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6058080) {
3646 		{ RCAR_GP_PIN(0,  7), 28, 2 },	/* QSPI1_MOSI_IO0 */
3647 		{ RCAR_GP_PIN(0,  6), 24, 2 },	/* QSPI1_SPCLK */
3648 		{ RCAR_GP_PIN(0,  5), 20, 2 },	/* QSPI0_SSL */
3649 		{ RCAR_GP_PIN(0,  4), 16, 2 },	/* QSPI0_IO3 */
3650 		{ RCAR_GP_PIN(0,  3), 12, 2 },	/* QSPI0_IO2 */
3651 		{ RCAR_GP_PIN(0,  2),  8, 2 },	/* QSPI0_MISO_IO1 */
3652 		{ RCAR_GP_PIN(0,  1),  4, 2 },	/* QSPI0_MOSI_IO0 */
3653 		{ RCAR_GP_PIN(0,  0),  0, 2 },	/* QSPI0_SPCLK */
3654 	} },
3655 	{ PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6058084) {
3656 		{ RCAR_GP_PIN(0, 15), 28, 3 },	/* SD_WP */
3657 		{ RCAR_GP_PIN(0, 14), 24, 2 },	/* RPC_INT_N */
3658 		{ RCAR_GP_PIN(0, 13), 20, 2 },	/* RPC_WP_N */
3659 		{ RCAR_GP_PIN(0, 12), 16, 2 },	/* RPC_RESET_N */
3660 		{ RCAR_GP_PIN(0, 11), 12, 2 },	/* QSPI1_SSL */
3661 		{ RCAR_GP_PIN(0, 10),  8, 2 },	/* QSPI1_IO3 */
3662 		{ RCAR_GP_PIN(0,  9),  4, 2 },	/* QSPI1_IO2 */
3663 		{ RCAR_GP_PIN(0,  8),  0, 2 },	/* QSPI1_MISO_IO1 */
3664 	} },
3665 	{ PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6058088) {
3666 		{ RCAR_GP_PIN(0, 23), 28, 3 },	/* MMC_SD_CLK */
3667 		{ RCAR_GP_PIN(0, 22), 24, 3 },	/* MMC_SD_D3 */
3668 		{ RCAR_GP_PIN(0, 21), 20, 3 },	/* MMC_SD_D2 */
3669 		{ RCAR_GP_PIN(0, 20), 16, 3 },	/* MMC_SD_D1 */
3670 		{ RCAR_GP_PIN(0, 19), 12, 3 },	/* MMC_SD_D0 */
3671 		{ RCAR_GP_PIN(0, 18),  8, 3 },	/* MMC_SD_CMD */
3672 		{ RCAR_GP_PIN(0, 17),  4, 3 },	/* MMC_DS */
3673 		{ RCAR_GP_PIN(0, 16),  0, 3 },	/* SD_CD */
3674 	} },
3675 	{ PINMUX_DRIVE_REG("DRV3CTRL0", 0xe605808c) {
3676 		{ RCAR_GP_PIN(0, 27), 12, 3 },	/* MMC_D7 */
3677 		{ RCAR_GP_PIN(0, 26),  8, 3 },	/* MMC_D6 */
3678 		{ RCAR_GP_PIN(0, 25),  4, 3 },	/* MMC_D5 */
3679 		{ RCAR_GP_PIN(0, 24),  0, 3 },	/* MMC_D4 */
3680 	} },
3681 	{ PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050080) {
3682 		{ RCAR_GP_PIN(1,  7), 28, 3 },	/* MSIOF0_TXD */
3683 		{ RCAR_GP_PIN(1,  6), 24, 3 },	/* MSIOF0_RXD */
3684 		{ RCAR_GP_PIN(1,  5), 20, 3 },	/* HTX0 */
3685 		{ RCAR_GP_PIN(1,  4), 16, 3 },	/* HCTS0_N */
3686 		{ RCAR_GP_PIN(1,  3), 12, 3 },	/* HRTS0_N */
3687 		{ RCAR_GP_PIN(1,  2),  8, 3 },	/* HSCK0 */
3688 		{ RCAR_GP_PIN(1,  1),  4, 3 },	/* HRX0 */
3689 		{ RCAR_GP_PIN(1,  0),  0, 3 },	/* SCIF_CLK */
3690 	} },
3691 	{ PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050084) {
3692 		{ RCAR_GP_PIN(1, 15), 28, 3 },	/* MSIOF1_SYNC */
3693 		{ RCAR_GP_PIN(1, 14), 24, 3 },	/* MSIOF1_SCK */
3694 		{ RCAR_GP_PIN(1, 13), 20, 3 },	/* MSIOF1_TXD */
3695 		{ RCAR_GP_PIN(1, 12), 16, 3 },	/* MSIOF1_RXD */
3696 		{ RCAR_GP_PIN(1, 11), 12, 3 },	/* MSIOF0_SS2 */
3697 		{ RCAR_GP_PIN(1, 10),  8, 3 },	/* MSIOF0_SS1 */
3698 		{ RCAR_GP_PIN(1,  9),  4, 3 },	/* MSIOF0_SYNC */
3699 		{ RCAR_GP_PIN(1,  8),  0, 3 },	/* MSIOF0_SCK */
3700 	} },
3701 	{ PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050088) {
3702 		{ RCAR_GP_PIN(1, 23), 28, 3 },	/* MSIOF2_SS2 */
3703 		{ RCAR_GP_PIN(1, 22), 24, 3 },	/* MSIOF2_SS1 */
3704 		{ RCAR_GP_PIN(1, 21), 20, 3 },	/* MSIOF2_SYNC */
3705 		{ RCAR_GP_PIN(1, 20), 16, 3 },	/* MSIOF2_SCK */
3706 		{ RCAR_GP_PIN(1, 19), 12, 3 },	/* MSIOF2_TXD */
3707 		{ RCAR_GP_PIN(1, 18),  8, 3 },	/* MSIOF2_RXD */
3708 		{ RCAR_GP_PIN(1, 17),  4, 3 },	/* MSIOF1_SS2 */
3709 		{ RCAR_GP_PIN(1, 16),  0, 3 },	/* MSIOF1_SS1 */
3710 	} },
3711 	{ PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605008c) {
3712 		{ RCAR_GP_PIN(1, 30), 24, 3 },	/* GP1_30 */
3713 		{ RCAR_GP_PIN(1, 29), 20, 3 },	/* GP1_29 */
3714 		{ RCAR_GP_PIN(1, 28), 16, 3 },	/* GP1_28 */
3715 		{ RCAR_GP_PIN(1, 27), 12, 3 },	/* IRQ3 */
3716 		{ RCAR_GP_PIN(1, 26),  8, 3 },	/* IRQ2 */
3717 		{ RCAR_GP_PIN(1, 25),  4, 3 },	/* IRQ1 */
3718 		{ RCAR_GP_PIN(1, 24),  0, 3 },	/* IRQ0 */
3719 	} },
3720 	{ PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6050880) {
3721 		{ RCAR_GP_PIN(2,  7), 28, 3 },	/* GP2_07 */
3722 		{ RCAR_GP_PIN(2,  6), 24, 3 },	/* GP2_06 */
3723 		{ RCAR_GP_PIN(2,  5), 20, 3 },	/* GP2_05 */
3724 		{ RCAR_GP_PIN(2,  4), 16, 3 },	/* GP2_04 */
3725 		{ RCAR_GP_PIN(2,  3), 12, 3 },	/* GP2_03 */
3726 		{ RCAR_GP_PIN(2,  2),  8, 3 },	/* GP2_02 */
3727 		{ RCAR_GP_PIN(2,  1),  4, 2 },	/* IPC_CLKOUT */
3728 		{ RCAR_GP_PIN(2,  0),  0, 2 },	/* IPC_CLKIN */
3729 	} },
3730 	{ PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6050884) {
3731 		{ RCAR_GP_PIN(2, 15), 28, 3 },	/* GP2_15 */
3732 		{ RCAR_GP_PIN(2, 14), 24, 3 },	/* GP2_14 */
3733 		{ RCAR_GP_PIN(2, 13), 20, 3 },	/* GP2_13 */
3734 		{ RCAR_GP_PIN(2, 12), 16, 3 },	/* GP2_12 */
3735 		{ RCAR_GP_PIN(2, 11), 12, 3 },	/* GP2_11 */
3736 		{ RCAR_GP_PIN(2, 10),  8, 3 },	/* GP2_10 */
3737 		{ RCAR_GP_PIN(2,  9),  4, 3 },	/* GP2_9 */
3738 		{ RCAR_GP_PIN(2,  8),  0, 3 },	/* GP2_8 */
3739 	} },
3740 	{ PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6050888) {
3741 		{ RCAR_GP_PIN(2, 23), 28, 3 },	/* TCLK1_A */
3742 		{ RCAR_GP_PIN(2, 22), 24, 3 },	/* TPU0TO1 */
3743 		{ RCAR_GP_PIN(2, 21), 20, 3 },	/* TPU0TO0 */
3744 		{ RCAR_GP_PIN(2, 20), 16, 3 },	/* CLK_EXTFXR */
3745 		{ RCAR_GP_PIN(2, 19), 12, 3 },	/* RXDB_EXTFXR */
3746 		{ RCAR_GP_PIN(2, 18),  8, 3 },	/* FXR_TXDB */
3747 		{ RCAR_GP_PIN(2, 17),  4, 3 },	/* RXDA_EXTFXR_A */
3748 		{ RCAR_GP_PIN(2, 16),  0, 3 },	/* FXR_TXDA_A */
3749 	} },
3750 	{ PINMUX_DRIVE_REG("DRV3CTRL2", 0xe605088c) {
3751 		{ RCAR_GP_PIN(2, 24), 0, 3 },	/* TCLK2_A */
3752 	} },
3753 	{ PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6058880) {
3754 		{ RCAR_GP_PIN(3,  7), 28, 3 },	/* CANFD3_TX */
3755 		{ RCAR_GP_PIN(3,  6), 24, 3 },	/* CANFD2_RX */
3756 		{ RCAR_GP_PIN(3,  5), 20, 3 },	/* CANFD2_TX */
3757 		{ RCAR_GP_PIN(3,  4), 16, 3 },	/* CANFD1_RX */
3758 		{ RCAR_GP_PIN(3,  3), 12, 3 },	/* CANFD1_TX */
3759 		{ RCAR_GP_PIN(3,  2),  8, 3 },	/* CANFD0_RX */
3760 		{ RCAR_GP_PIN(3,  1),  4, 2 },	/* CANFD0_TX */
3761 		{ RCAR_GP_PIN(3,  0),  0, 2 },	/* CAN_CLK */
3762 	} },
3763 	{ PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6058884) {
3764 		{ RCAR_GP_PIN(3, 15), 28, 3 },	/* CANFD7_TX */
3765 		{ RCAR_GP_PIN(3, 14), 24, 3 },	/* CANFD6_RX */
3766 		{ RCAR_GP_PIN(3, 13), 20, 3 },	/* CANFD6_TX */
3767 		{ RCAR_GP_PIN(3, 12), 16, 3 },	/* CANFD5_RX */
3768 		{ RCAR_GP_PIN(3, 11), 12, 3 },	/* CANFD5_TX */
3769 		{ RCAR_GP_PIN(3, 10),  8, 3 },	/* CANFD4_RX */
3770 		{ RCAR_GP_PIN(3,  9),  4, 3 },	/* CANFD4_TX */
3771 		{ RCAR_GP_PIN(3,  8),  0, 3 },	/* CANFD3_RX */
3772 	} },
3773 	{ PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) {
3774 		{ RCAR_GP_PIN(3,  16),  0, 3 },	/* CANFD7_RX */
3775 	} },
3776 	{ PINMUX_DRIVE_REG("DRV0CTRL4", 0xe6060080) {
3777 		{ RCAR_GP_PIN(4,  7), 28, 3 },	/* AVB0_TXC */
3778 		{ RCAR_GP_PIN(4,  6), 24, 3 },	/* AVB0_TX_CTL */
3779 		{ RCAR_GP_PIN(4,  5), 20, 3 },	/* AVB0_RD3 */
3780 		{ RCAR_GP_PIN(4,  4), 16, 3 },	/* AVB0_RD2 */
3781 		{ RCAR_GP_PIN(4,  3), 12, 3 },	/* AVB0_RD1 */
3782 		{ RCAR_GP_PIN(4,  2),  8, 3 },	/* AVB0_RD0 */
3783 		{ RCAR_GP_PIN(4,  1),  4, 3 },	/* AVB0_RXC */
3784 		{ RCAR_GP_PIN(4,  0),  0, 3 },	/* AVB0_RX_CTL */
3785 	} },
3786 	{ PINMUX_DRIVE_REG("DRV1CTRL4", 0xe6060084) {
3787 		{ RCAR_GP_PIN(4, 15), 28, 3 },	/* AVB0_MAGIC */
3788 		{ RCAR_GP_PIN(4, 14), 24, 3 },	/* AVB0_MDC */
3789 		{ RCAR_GP_PIN(4, 13), 20, 3 },	/* AVB0_MDIO */
3790 		{ RCAR_GP_PIN(4, 12), 16, 3 },	/* AVB0_TXCREFCLK */
3791 		{ RCAR_GP_PIN(4, 11), 12, 3 },	/* AVB0_TD3 */
3792 		{ RCAR_GP_PIN(4, 10),  8, 3 },	/* AVB0_TD2 */
3793 		{ RCAR_GP_PIN(4,  9),  4, 3 },	/* AVB0_TD1*/
3794 		{ RCAR_GP_PIN(4,  8),  0, 3 },	/* AVB0_TD0 */
3795 	} },
3796 	{ PINMUX_DRIVE_REG("DRV2CTRL4", 0xe6060088) {
3797 		{ RCAR_GP_PIN(4, 23), 28, 3 },	/* PCIE2_CLKREQ_N */
3798 		{ RCAR_GP_PIN(4, 22), 24, 3 },	/* PCIE1_CLKREQ_N */
3799 		{ RCAR_GP_PIN(4, 21), 20, 3 },	/* PCIE0_CLKREQ_N */
3800 		{ RCAR_GP_PIN(4, 20), 16, 3 },	/* AVB0_AVTP_PPS */
3801 		{ RCAR_GP_PIN(4, 19), 12, 3 },	/* AVB0_AVTP_CAPTURE */
3802 		{ RCAR_GP_PIN(4, 18),  8, 3 },	/* AVB0_AVTP_MATCH */
3803 		{ RCAR_GP_PIN(4, 17),  4, 3 },	/* AVB0_LINK */
3804 		{ RCAR_GP_PIN(4, 16),  0, 3 },	/* AVB0_PHY_INT */
3805 	} },
3806 	{ PINMUX_DRIVE_REG("DRV3CTRL4", 0xe606008c) {
3807 		{ RCAR_GP_PIN(4, 26),  8, 3 },	/* AVS1 */
3808 		{ RCAR_GP_PIN(4, 25),  4, 3 },	/* AVS0 */
3809 		{ RCAR_GP_PIN(4, 24),  0, 3 },	/* PCIE3_CLKREQ_N */
3810 	} },
3811 	{ PINMUX_DRIVE_REG("DRV0CTRL5", 0xe6060880) {
3812 		{ RCAR_GP_PIN(5,  7), 28, 3 },	/* AVB1_TXC */
3813 		{ RCAR_GP_PIN(5,  6), 24, 3 },	/* AVB1_TX_CTL */
3814 		{ RCAR_GP_PIN(5,  5), 20, 3 },	/* AVB1_RD3 */
3815 		{ RCAR_GP_PIN(5,  4), 16, 3 },	/* AVB1_RD2 */
3816 		{ RCAR_GP_PIN(5,  3), 12, 3 },	/* AVB1_RD1 */
3817 		{ RCAR_GP_PIN(5,  2),  8, 3 },	/* AVB1_RD0 */
3818 		{ RCAR_GP_PIN(5,  1),  4, 3 },	/* AVB1_RXC */
3819 		{ RCAR_GP_PIN(5,  0),  0, 3 },	/* AVB1_RX_CTL */
3820 	} },
3821 	{ PINMUX_DRIVE_REG("DRV1CTRL5", 0xe6060884) {
3822 		{ RCAR_GP_PIN(5, 15), 28, 3 },	/* AVB1_MAGIC */
3823 		{ RCAR_GP_PIN(5, 14), 24, 3 },	/* AVB1_MDC */
3824 		{ RCAR_GP_PIN(5, 13), 20, 3 },	/* AVB1_MDIO */
3825 		{ RCAR_GP_PIN(5, 12), 16, 3 },	/* AVB1_TXCREFCLK */
3826 		{ RCAR_GP_PIN(5, 11), 12, 3 },	/* AVB1_TD3 */
3827 		{ RCAR_GP_PIN(5, 10),  8, 3 },	/* AVB1_TD2 */
3828 		{ RCAR_GP_PIN(5,  9),  4, 3 },	/* AVB1_TD1*/
3829 		{ RCAR_GP_PIN(5,  8),  0, 3 },	/* AVB1_TD0 */
3830 	} },
3831 	{ PINMUX_DRIVE_REG("DRV2CTRL5", 0xe6060888) {
3832 		{ RCAR_GP_PIN(5, 20), 16, 3 },	/* AVB1_AVTP_PPS */
3833 		{ RCAR_GP_PIN(5, 19), 12, 3 },	/* AVB1_AVTP_CAPTURE */
3834 		{ RCAR_GP_PIN(5, 18),  8, 3 },	/* AVB1_AVTP_MATCH */
3835 		{ RCAR_GP_PIN(5, 17),  4, 3 },	/* AVB1_LINK */
3836 		{ RCAR_GP_PIN(5, 16),  0, 3 },	/* AVB1_PHY_INT */
3837 	} },
3838 	{ PINMUX_DRIVE_REG("DRV0CTRL6", 0xe6068080) {
3839 		{ RCAR_GP_PIN(6,  7), 28, 3 },	/* AVB2_TXC */
3840 		{ RCAR_GP_PIN(6,  6), 24, 3 },	/* AVB2_TX_CTL */
3841 		{ RCAR_GP_PIN(6,  5), 20, 3 },	/* AVB2_RD3 */
3842 		{ RCAR_GP_PIN(6,  4), 16, 3 },	/* AVB2_RD2 */
3843 		{ RCAR_GP_PIN(6,  3), 12, 3 },	/* AVB2_RD1 */
3844 		{ RCAR_GP_PIN(6,  2),  8, 3 },	/* AVB2_RD0 */
3845 		{ RCAR_GP_PIN(6,  1),  4, 3 },	/* AVB2_RXC */
3846 		{ RCAR_GP_PIN(6,  0),  0, 3 },	/* AVB2_RX_CTL */
3847 	} },
3848 	{ PINMUX_DRIVE_REG("DRV1CTRL6", 0xe6068084) {
3849 		{ RCAR_GP_PIN(6, 15), 28, 3 },	/* AVB2_MAGIC */
3850 		{ RCAR_GP_PIN(6, 14), 24, 3 },	/* AVB2_MDC */
3851 		{ RCAR_GP_PIN(6, 13), 20, 3 },	/* AVB2_MDIO */
3852 		{ RCAR_GP_PIN(6, 12), 16, 3 },	/* AVB2_TXCREFCLK */
3853 		{ RCAR_GP_PIN(6, 11), 12, 3 },	/* AVB2_TD3 */
3854 		{ RCAR_GP_PIN(6, 10),  8, 3 },	/* AVB2_TD2 */
3855 		{ RCAR_GP_PIN(6,  9),  4, 3 },	/* AVB2_TD1*/
3856 		{ RCAR_GP_PIN(6,  8),  0, 3 },	/* AVB2_TD0 */
3857 	} },
3858 	{ PINMUX_DRIVE_REG("DRV2CTRL6", 0xe6068088) {
3859 		{ RCAR_GP_PIN(6, 20), 16, 3 },	/* AVB2_AVTP_PPS */
3860 		{ RCAR_GP_PIN(6, 19), 12, 3 },	/* AVB2_AVTP_CAPTURE */
3861 		{ RCAR_GP_PIN(6, 18),  8, 3 },	/* AVB2_AVTP_MATCH */
3862 		{ RCAR_GP_PIN(6, 17),  4, 3 },	/* AVB2_LINK */
3863 		{ RCAR_GP_PIN(6, 16),  0, 3 },	/* AVB2_PHY_INT */
3864 	} },
3865 	{ PINMUX_DRIVE_REG("DRV0CTRL7", 0xe6068880) {
3866 		{ RCAR_GP_PIN(7,  7), 28, 3 },	/* AVB3_TXC */
3867 		{ RCAR_GP_PIN(7,  6), 24, 3 },	/* AVB3_TX_CTL */
3868 		{ RCAR_GP_PIN(7,  5), 20, 3 },	/* AVB3_RD3 */
3869 		{ RCAR_GP_PIN(7,  4), 16, 3 },	/* AVB3_RD2 */
3870 		{ RCAR_GP_PIN(7,  3), 12, 3 },	/* AVB3_RD1 */
3871 		{ RCAR_GP_PIN(7,  2),  8, 3 },	/* AVB3_RD0 */
3872 		{ RCAR_GP_PIN(7,  1),  4, 3 },	/* AVB3_RXC */
3873 		{ RCAR_GP_PIN(7,  0),  0, 3 },	/* AVB3_RX_CTL */
3874 	} },
3875 	{ PINMUX_DRIVE_REG("DRV1CTRL7", 0xe6068884) {
3876 		{ RCAR_GP_PIN(7, 15), 28, 3 },	/* AVB3_MAGIC */
3877 		{ RCAR_GP_PIN(7, 14), 24, 3 },	/* AVB3_MDC */
3878 		{ RCAR_GP_PIN(7, 13), 20, 3 },	/* AVB3_MDIO */
3879 		{ RCAR_GP_PIN(7, 12), 16, 3 },	/* AVB3_TXCREFCLK */
3880 		{ RCAR_GP_PIN(7, 11), 12, 3 },	/* AVB3_TD3 */
3881 		{ RCAR_GP_PIN(7, 10),  8, 3 },	/* AVB3_TD2 */
3882 		{ RCAR_GP_PIN(7,  9),  4, 3 },	/* AVB3_TD1*/
3883 		{ RCAR_GP_PIN(7,  8),  0, 3 },	/* AVB3_TD0 */
3884 	} },
3885 	{ PINMUX_DRIVE_REG("DRV2CTRL7", 0xe6068888) {
3886 		{ RCAR_GP_PIN(7, 20), 16, 3 },	/* AVB3_AVTP_PPS */
3887 		{ RCAR_GP_PIN(7, 19), 12, 3 },	/* AVB3_AVTP_CAPTURE */
3888 		{ RCAR_GP_PIN(7, 18),  8, 3 },	/* AVB3_AVTP_MATCH */
3889 		{ RCAR_GP_PIN(7, 17),  4, 3 },	/* AVB3_LINK */
3890 		{ RCAR_GP_PIN(7, 16),  0, 3 },	/* AVB3_PHY_INT */
3891 	} },
3892 	{ PINMUX_DRIVE_REG("DRV0CTRL8", 0xe6069080) {
3893 		{ RCAR_GP_PIN(8,  7), 28, 3 },	/* AVB4_TXC */
3894 		{ RCAR_GP_PIN(8,  6), 24, 3 },	/* AVB4_TX_CTL */
3895 		{ RCAR_GP_PIN(8,  5), 20, 3 },	/* AVB4_RD3 */
3896 		{ RCAR_GP_PIN(8,  4), 16, 3 },	/* AVB4_RD2 */
3897 		{ RCAR_GP_PIN(8,  3), 12, 3 },	/* AVB4_RD1 */
3898 		{ RCAR_GP_PIN(8,  2),  8, 3 },	/* AVB4_RD0 */
3899 		{ RCAR_GP_PIN(8,  1),  4, 3 },	/* AVB4_RXC */
3900 		{ RCAR_GP_PIN(8,  0),  0, 3 },	/* AVB4_RX_CTL */
3901 	} },
3902 	{ PINMUX_DRIVE_REG("DRV1CTRL8", 0xe6069084) {
3903 		{ RCAR_GP_PIN(8, 15), 28, 3 },	/* AVB4_MAGIC */
3904 		{ RCAR_GP_PIN(8, 14), 24, 3 },	/* AVB4_MDC */
3905 		{ RCAR_GP_PIN(8, 13), 20, 3 },	/* AVB4_MDIO */
3906 		{ RCAR_GP_PIN(8, 12), 16, 3 },	/* AVB4_TXCREFCLK */
3907 		{ RCAR_GP_PIN(8, 11), 12, 3 },	/* AVB4_TD3 */
3908 		{ RCAR_GP_PIN(8, 10),  8, 3 },	/* AVB4_TD2 */
3909 		{ RCAR_GP_PIN(8,  9),  4, 3 },	/* AVB4_TD1*/
3910 		{ RCAR_GP_PIN(8,  8),  0, 3 },	/* AVB4_TD0 */
3911 	} },
3912 	{ PINMUX_DRIVE_REG("DRV2CTRL8", 0xe6069088) {
3913 		{ RCAR_GP_PIN(8, 20), 16, 3 },	/* AVB4_AVTP_PPS */
3914 		{ RCAR_GP_PIN(8, 19), 12, 3 },	/* AVB4_AVTP_CAPTURE */
3915 		{ RCAR_GP_PIN(8, 18),  8, 3 },	/* AVB4_AVTP_MATCH */
3916 		{ RCAR_GP_PIN(8, 17),  4, 3 },	/* AVB4_LINK */
3917 		{ RCAR_GP_PIN(8, 16),  0, 3 },	/* AVB4_PHY_INT */
3918 	} },
3919 	{ PINMUX_DRIVE_REG("DRV0CTRL9", 0xe6069880) {
3920 		{ RCAR_GP_PIN(9,  7), 28, 3 },	/* AVB5_TXC */
3921 		{ RCAR_GP_PIN(9,  6), 24, 3 },	/* AVB5_TX_CTL */
3922 		{ RCAR_GP_PIN(9,  5), 20, 3 },	/* AVB5_RD3 */
3923 		{ RCAR_GP_PIN(9,  4), 16, 3 },	/* AVB5_RD2 */
3924 		{ RCAR_GP_PIN(9,  3), 12, 3 },	/* AVB5_RD1 */
3925 		{ RCAR_GP_PIN(9,  2),  8, 3 },	/* AVB5_RD0 */
3926 		{ RCAR_GP_PIN(9,  1),  4, 3 },	/* AVB5_RXC */
3927 		{ RCAR_GP_PIN(9,  0),  0, 3 },	/* AVB5_RX_CTL */
3928 	} },
3929 	{ PINMUX_DRIVE_REG("DRV1CTRL9", 0xe6069884) {
3930 		{ RCAR_GP_PIN(9, 15), 28, 3 },	/* AVB5_MAGIC */
3931 		{ RCAR_GP_PIN(9, 14), 24, 3 },	/* AVB5_MDC */
3932 		{ RCAR_GP_PIN(9, 13), 20, 3 },	/* AVB5_MDIO */
3933 		{ RCAR_GP_PIN(9, 12), 16, 3 },	/* AVB5_TXCREFCLK */
3934 		{ RCAR_GP_PIN(9, 11), 12, 3 },	/* AVB5_TD3 */
3935 		{ RCAR_GP_PIN(9, 10),  8, 3 },	/* AVB5_TD2 */
3936 		{ RCAR_GP_PIN(9,  9),  4, 3 },	/* AVB5_TD1*/
3937 		{ RCAR_GP_PIN(9,  8),  0, 3 },	/* AVB5_TD0 */
3938 	} },
3939 	{ PINMUX_DRIVE_REG("DRV2CTRL9", 0xe6069888) {
3940 		{ RCAR_GP_PIN(9, 20), 16, 3 },	/* AVB5_AVTP_PPS */
3941 		{ RCAR_GP_PIN(9, 19), 12, 3 },	/* AVB5_AVTP_CAPTURE */
3942 		{ RCAR_GP_PIN(9, 18),  8, 3 },	/* AVB5_AVTP_MATCH */
3943 		{ RCAR_GP_PIN(9, 17),  4, 3 },	/* AVB5_LINK */
3944 		{ RCAR_GP_PIN(9, 16),  0, 3 },	/* AVB5_PHY_INT */
3945 	} },
3946 	{ },
3947 };
3948 
3949 enum ioctrl_regs {
3950 	POC0,
3951 	POC1,
3952 	POC2,
3953 	POC4,
3954 	POC5,
3955 	POC6,
3956 	POC7,
3957 	POC8,
3958 	POC9,
3959 	TD1SEL0,
3960 };
3961 
3962 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3963 	[POC0] = { 0xe60580a0, },
3964 	[POC1] = { 0xe60500a0, },
3965 	[POC2] = { 0xe60508a0, },
3966 	[POC4] = { 0xe60600a0, },
3967 	[POC5] = { 0xe60608a0, },
3968 	[POC6] = { 0xe60680a0, },
3969 	[POC7] = { 0xe60688a0, },
3970 	[POC8] = { 0xe60690a0, },
3971 	[POC9] = { 0xe60698a0, },
3972 	[TD1SEL0] = { 0xe6058124, },
3973 	{ /* sentinel */ },
3974 };
3975 
r8a779a0_pin_to_pocctrl(unsigned int pin,u32 * pocctrl)3976 static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
3977 {
3978 	int bit = pin & 0x1f;
3979 
3980 	*pocctrl = pinmux_ioctrl_regs[POC0].reg;
3981 	if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27))
3982 		return bit;
3983 
3984 	*pocctrl = pinmux_ioctrl_regs[POC1].reg;
3985 	if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30))
3986 		return bit;
3987 
3988 	*pocctrl = pinmux_ioctrl_regs[POC2].reg;
3989 	if (pin >= RCAR_GP_PIN(2, 2) && pin <= RCAR_GP_PIN(2, 15))
3990 		return bit;
3991 
3992 	*pocctrl = pinmux_ioctrl_regs[POC4].reg;
3993 	if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
3994 		return bit;
3995 
3996 	*pocctrl = pinmux_ioctrl_regs[POC5].reg;
3997 	if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17))
3998 		return bit;
3999 
4000 	*pocctrl = pinmux_ioctrl_regs[POC6].reg;
4001 	if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17))
4002 		return bit;
4003 
4004 	*pocctrl = pinmux_ioctrl_regs[POC7].reg;
4005 	if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17))
4006 		return bit;
4007 
4008 	*pocctrl = pinmux_ioctrl_regs[POC8].reg;
4009 	if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17))
4010 		return bit;
4011 
4012 	*pocctrl = pinmux_ioctrl_regs[POC9].reg;
4013 	if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17))
4014 		return bit;
4015 
4016 	return -EINVAL;
4017 }
4018 
4019 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4020 	{ PINMUX_BIAS_REG("PUEN0", 0xe60580c0, "PUD0", 0xe60580e0) {
4021 		[ 0] = RCAR_GP_PIN(0,  0),	/* QSPI0_SPCLK */
4022 		[ 1] = RCAR_GP_PIN(0,  1),	/* QSPI0_MOSI_IO0 */
4023 		[ 2] = RCAR_GP_PIN(0,  2),	/* QSPI0_MISO_IO1 */
4024 		[ 3] = RCAR_GP_PIN(0,  3),	/* QSPI0_IO2 */
4025 		[ 4] = RCAR_GP_PIN(0,  4),	/* QSPI0_IO3 */
4026 		[ 5] = RCAR_GP_PIN(0,  5),	/* QSPI0_SSL */
4027 		[ 6] = RCAR_GP_PIN(0,  6),	/* QSPI1_SPCLK */
4028 		[ 7] = RCAR_GP_PIN(0,  7),	/* QSPI1_MOSI_IO0 */
4029 		[ 8] = RCAR_GP_PIN(0,  8),	/* QSPI1_MISO_IO1 */
4030 		[ 9] = RCAR_GP_PIN(0,  9),	/* QSPI1_IO2 */
4031 		[10] = RCAR_GP_PIN(0, 10),	/* QSPI1_IO3 */
4032 		[11] = RCAR_GP_PIN(0, 11),	/* QSPI1_SSL */
4033 		[12] = RCAR_GP_PIN(0, 12),	/* RPC_RESET_N */
4034 		[13] = RCAR_GP_PIN(0, 13),	/* RPC_WP_N */
4035 		[14] = RCAR_GP_PIN(0, 14),	/* RPC_INT_N */
4036 		[15] = RCAR_GP_PIN(0, 15),	/* SD_WP */
4037 		[16] = RCAR_GP_PIN(0, 16),	/* SD_CD */
4038 		[17] = RCAR_GP_PIN(0, 17),	/* MMC_DS */
4039 		[18] = RCAR_GP_PIN(0, 18),	/* MMC_SD_CMD */
4040 		[19] = RCAR_GP_PIN(0, 19),	/* MMC_SD_D0 */
4041 		[20] = RCAR_GP_PIN(0, 20),	/* MMC_SD_D1 */
4042 		[21] = RCAR_GP_PIN(0, 21),	/* MMC_SD_D2 */
4043 		[22] = RCAR_GP_PIN(0, 22),	/* MMC_SD_D3 */
4044 		[23] = RCAR_GP_PIN(0, 23),	/* MMC_SD_CLK */
4045 		[24] = RCAR_GP_PIN(0, 24),	/* MMC_D4 */
4046 		[25] = RCAR_GP_PIN(0, 25),	/* MMC_D5 */
4047 		[26] = RCAR_GP_PIN(0, 26),	/* MMC_D6 */
4048 		[27] = RCAR_GP_PIN(0, 27),	/* MMC_D7 */
4049 		[28] = SH_PFC_PIN_NONE,
4050 		[29] = SH_PFC_PIN_NONE,
4051 		[30] = SH_PFC_PIN_NONE,
4052 		[31] = SH_PFC_PIN_NONE,
4053 	} },
4054 	{ PINMUX_BIAS_REG("PUEN1", 0xe60500c0, "PUD1", 0xe60500e0) {
4055 		[ 0] = RCAR_GP_PIN(1,  0),	/* SCIF_CLK */
4056 		[ 1] = RCAR_GP_PIN(1,  1),	/* HRX0 */
4057 		[ 2] = RCAR_GP_PIN(1,  2),	/* HSCK0 */
4058 		[ 3] = RCAR_GP_PIN(1,  3),	/* HRTS0_N */
4059 		[ 4] = RCAR_GP_PIN(1,  4),	/* HCTS0_N */
4060 		[ 5] = RCAR_GP_PIN(1,  5),	/* HTX0 */
4061 		[ 6] = RCAR_GP_PIN(1,  6),	/* MSIOF0_RXD */
4062 		[ 7] = RCAR_GP_PIN(1,  7),	/* MSIOF0_TXD */
4063 		[ 8] = RCAR_GP_PIN(1,  8),	/* MSIOF0_SCK */
4064 		[ 9] = RCAR_GP_PIN(1,  9),	/* MSIOF0_SYNC */
4065 		[10] = RCAR_GP_PIN(1, 10),	/* MSIOF0_SS1 */
4066 		[11] = RCAR_GP_PIN(1, 11),	/* MSIOF0_SS2 */
4067 		[12] = RCAR_GP_PIN(1, 12),	/* MSIOF1_RXD */
4068 		[13] = RCAR_GP_PIN(1, 13),	/* MSIOF1_TXD */
4069 		[14] = RCAR_GP_PIN(1, 14),	/* MSIOF1_SCK */
4070 		[15] = RCAR_GP_PIN(1, 15),	/* MSIOF1_SYNC */
4071 		[16] = RCAR_GP_PIN(1, 16),	/* MSIOF1_SS1 */
4072 		[17] = RCAR_GP_PIN(1, 17),	/* MSIOF1_SS2 */
4073 		[18] = RCAR_GP_PIN(1, 18),	/* MSIOF2_RXD */
4074 		[19] = RCAR_GP_PIN(1, 19),	/* MSIOF2_TXD */
4075 		[20] = RCAR_GP_PIN(1, 20),	/* MSIOF2_SCK */
4076 		[21] = RCAR_GP_PIN(1, 21),	/* MSIOF2_SYNC */
4077 		[22] = RCAR_GP_PIN(1, 22),	/* MSIOF2_SS1 */
4078 		[23] = RCAR_GP_PIN(1, 23),	/* MSIOF2_SS2 */
4079 		[24] = RCAR_GP_PIN(1, 24),	/* IRQ0 */
4080 		[25] = RCAR_GP_PIN(1, 25),	/* IRQ1 */
4081 		[26] = RCAR_GP_PIN(1, 26),	/* IRQ2 */
4082 		[27] = RCAR_GP_PIN(1, 27),	/* IRQ3 */
4083 		[28] = RCAR_GP_PIN(1, 28),	/* GP1_28 */
4084 		[29] = RCAR_GP_PIN(1, 29),	/* GP1_29 */
4085 		[30] = RCAR_GP_PIN(1, 30),	/* GP1_30 */
4086 		[31] = SH_PFC_PIN_NONE,
4087 	} },
4088 	{ PINMUX_BIAS_REG("PUEN2", 0xe60508c0, "PUD2", 0xe60508e0) {
4089 		[ 0] = RCAR_GP_PIN(2,  0),	/* IPC_CLKIN */
4090 		[ 1] = RCAR_GP_PIN(2,  1),	/* IPC_CLKOUT */
4091 		[ 2] = RCAR_GP_PIN(2,  2),	/* GP2_02 */
4092 		[ 3] = RCAR_GP_PIN(2,  3),	/* GP2_03 */
4093 		[ 4] = RCAR_GP_PIN(2,  4),	/* GP2_04 */
4094 		[ 5] = RCAR_GP_PIN(2,  5),	/* GP2_05 */
4095 		[ 6] = RCAR_GP_PIN(2,  6),	/* GP2_06 */
4096 		[ 7] = RCAR_GP_PIN(2,  7),	/* GP2_07 */
4097 		[ 8] = RCAR_GP_PIN(2,  8),	/* GP2_08 */
4098 		[ 9] = RCAR_GP_PIN(2,  9),	/* GP2_09 */
4099 		[10] = RCAR_GP_PIN(2, 10),	/* GP2_10 */
4100 		[11] = RCAR_GP_PIN(2, 11),	/* GP2_11 */
4101 		[12] = RCAR_GP_PIN(2, 12),	/* GP2_12 */
4102 		[13] = RCAR_GP_PIN(2, 13),	/* GP2_13 */
4103 		[14] = RCAR_GP_PIN(2, 14),	/* GP2_14 */
4104 		[15] = RCAR_GP_PIN(2, 15),	/* GP2_15 */
4105 		[16] = RCAR_GP_PIN(2, 16),	/* FXR_TXDA_A */
4106 		[17] = RCAR_GP_PIN(2, 17),	/* RXDA_EXTFXR_A */
4107 		[18] = RCAR_GP_PIN(2, 18),	/* FXR_TXDB */
4108 		[19] = RCAR_GP_PIN(2, 19),	/* RXDB_EXTFXR */
4109 		[20] = RCAR_GP_PIN(2, 20),	/* CLK_EXTFXR */
4110 		[21] = RCAR_GP_PIN(2, 21),	/* TPU0TO0 */
4111 		[22] = RCAR_GP_PIN(2, 22),	/* TPU0TO1 */
4112 		[23] = RCAR_GP_PIN(2, 23),	/* TCLK1_A */
4113 		[24] = RCAR_GP_PIN(2, 24),	/* TCLK2_A */
4114 		[25] = SH_PFC_PIN_NONE,
4115 		[26] = SH_PFC_PIN_NONE,
4116 		[27] = SH_PFC_PIN_NONE,
4117 		[28] = SH_PFC_PIN_NONE,
4118 		[29] = SH_PFC_PIN_NONE,
4119 		[30] = SH_PFC_PIN_NONE,
4120 		[31] = SH_PFC_PIN_NONE,
4121 	} },
4122 	{ PINMUX_BIAS_REG("PUEN3", 0xe60588c0, "PUD3", 0xe60588e0) {
4123 		[ 0] = RCAR_GP_PIN(3,  0),	/* CAN_CLK */
4124 		[ 1] = RCAR_GP_PIN(3,  1),	/* CANFD0_TX */
4125 		[ 2] = RCAR_GP_PIN(3,  2),	/* CANFD0_RX */
4126 		[ 3] = RCAR_GP_PIN(3,  3),	/* CANFD1_TX */
4127 		[ 4] = RCAR_GP_PIN(3,  4),	/* CANFD1_RX */
4128 		[ 5] = RCAR_GP_PIN(3,  5),	/* CANFD2_TX */
4129 		[ 6] = RCAR_GP_PIN(3,  6),	/* CANFD2_RX */
4130 		[ 7] = RCAR_GP_PIN(3,  7),	/* CANFD3_TX */
4131 		[ 8] = RCAR_GP_PIN(3,  8),	/* CANFD3_RX */
4132 		[ 9] = RCAR_GP_PIN(3,  9),	/* CANFD4_TX */
4133 		[10] = RCAR_GP_PIN(3, 10),	/* CANFD4_RX */
4134 		[11] = RCAR_GP_PIN(3, 11),	/* CANFD5_TX */
4135 		[12] = RCAR_GP_PIN(3, 12),	/* CANFD5_RX */
4136 		[13] = RCAR_GP_PIN(3, 13),	/* CANFD6_TX */
4137 		[14] = RCAR_GP_PIN(3, 14),	/* CANFD6_RX */
4138 		[15] = RCAR_GP_PIN(3, 15),	/* CANFD7_TX */
4139 		[16] = RCAR_GP_PIN(3, 16),	/* CANFD7_RX */
4140 		[17] = SH_PFC_PIN_NONE,
4141 		[18] = SH_PFC_PIN_NONE,
4142 		[19] = SH_PFC_PIN_NONE,
4143 		[20] = SH_PFC_PIN_NONE,
4144 		[21] = SH_PFC_PIN_NONE,
4145 		[22] = SH_PFC_PIN_NONE,
4146 		[23] = SH_PFC_PIN_NONE,
4147 		[24] = SH_PFC_PIN_NONE,
4148 		[25] = SH_PFC_PIN_NONE,
4149 		[26] = SH_PFC_PIN_NONE,
4150 		[27] = SH_PFC_PIN_NONE,
4151 		[28] = SH_PFC_PIN_NONE,
4152 		[29] = SH_PFC_PIN_NONE,
4153 		[30] = SH_PFC_PIN_NONE,
4154 		[31] = SH_PFC_PIN_NONE,
4155 	} },
4156 	{ PINMUX_BIAS_REG("PUEN4", 0xe60600c0, "PUD4", 0xe60600e0) {
4157 		[ 0] = RCAR_GP_PIN(4,  0),	/* AVB0_RX_CTL */
4158 		[ 1] = RCAR_GP_PIN(4,  1),	/* AVB0_RXC */
4159 		[ 2] = RCAR_GP_PIN(4,  2),	/* AVB0_RD0 */
4160 		[ 3] = RCAR_GP_PIN(4,  3),	/* AVB0_RD1 */
4161 		[ 4] = RCAR_GP_PIN(4,  4),	/* AVB0_RD2 */
4162 		[ 5] = RCAR_GP_PIN(4,  5),	/* AVB0_RD3 */
4163 		[ 6] = RCAR_GP_PIN(4,  6),	/* AVB0_TX_CTL */
4164 		[ 7] = RCAR_GP_PIN(4,  7),	/* AVB0_TXC */
4165 		[ 8] = RCAR_GP_PIN(4,  8),	/* AVB0_TD0 */
4166 		[ 9] = RCAR_GP_PIN(4,  9),	/* AVB0_TD1 */
4167 		[10] = RCAR_GP_PIN(4, 10),	/* AVB0_TD2 */
4168 		[11] = RCAR_GP_PIN(4, 11),	/* AVB0_TD3 */
4169 		[12] = RCAR_GP_PIN(4, 12),	/* AVB0_TXREFCLK */
4170 		[13] = RCAR_GP_PIN(4, 13),	/* AVB0_MDIO */
4171 		[14] = RCAR_GP_PIN(4, 14),	/* AVB0_MDC */
4172 		[15] = RCAR_GP_PIN(4, 15),	/* AVB0_MAGIC */
4173 		[16] = RCAR_GP_PIN(4, 16),	/* AVB0_PHY_INT */
4174 		[17] = RCAR_GP_PIN(4, 17),	/* AVB0_LINK */
4175 		[18] = RCAR_GP_PIN(4, 18),	/* AVB0_AVTP_MATCH */
4176 		[19] = RCAR_GP_PIN(4, 19),	/* AVB0_AVTP_CAPTURE */
4177 		[20] = RCAR_GP_PIN(4, 20),	/* AVB0_AVTP_PPS */
4178 		[21] = RCAR_GP_PIN(4, 21),	/* PCIE0_CLKREQ_N */
4179 		[22] = RCAR_GP_PIN(4, 22),	/* PCIE1_CLKREQ_N */
4180 		[23] = RCAR_GP_PIN(4, 23),	/* PCIE2_CLKREQ_N */
4181 		[24] = RCAR_GP_PIN(4, 24),	/* PCIE3_CLKREQ_N */
4182 		[25] = RCAR_GP_PIN(4, 25),	/* AVS0 */
4183 		[26] = RCAR_GP_PIN(4, 26),	/* AVS1 */
4184 		[27] = SH_PFC_PIN_NONE,
4185 		[28] = SH_PFC_PIN_NONE,
4186 		[29] = SH_PFC_PIN_NONE,
4187 		[30] = SH_PFC_PIN_NONE,
4188 		[31] = SH_PFC_PIN_NONE,
4189 	} },
4190 	{ PINMUX_BIAS_REG("PUEN5", 0xe60608c0, "PUD5", 0xe60608e0) {
4191 		[ 0] = RCAR_GP_PIN(5,  0),	/* AVB1_RX_CTL */
4192 		[ 1] = RCAR_GP_PIN(5,  1),	/* AVB1_RXC */
4193 		[ 2] = RCAR_GP_PIN(5,  2),	/* AVB1_RD0 */
4194 		[ 3] = RCAR_GP_PIN(5,  3),	/* AVB1_RD1 */
4195 		[ 4] = RCAR_GP_PIN(5,  4),	/* AVB1_RD2 */
4196 		[ 5] = RCAR_GP_PIN(5,  5),	/* AVB1_RD3 */
4197 		[ 6] = RCAR_GP_PIN(5,  6),	/* AVB1_TX_CTL */
4198 		[ 7] = RCAR_GP_PIN(5,  7),	/* AVB1_TXC */
4199 		[ 8] = RCAR_GP_PIN(5,  8),	/* AVB1_TD0 */
4200 		[ 9] = RCAR_GP_PIN(5,  9),	/* AVB1_TD1 */
4201 		[10] = RCAR_GP_PIN(5, 10),	/* AVB1_TD2 */
4202 		[11] = RCAR_GP_PIN(5, 11),	/* AVB1_TD3 */
4203 		[12] = RCAR_GP_PIN(5, 12),	/* AVB1_TXCREFCLK */
4204 		[13] = RCAR_GP_PIN(5, 13),	/* AVB1_MDIO */
4205 		[14] = RCAR_GP_PIN(5, 14),	/* AVB1_MDC */
4206 		[15] = RCAR_GP_PIN(5, 15),	/* AVB1_MAGIC */
4207 		[16] = RCAR_GP_PIN(5, 16),	/* AVB1_PHY_INT */
4208 		[17] = RCAR_GP_PIN(5, 17),	/* AVB1_LINK */
4209 		[18] = RCAR_GP_PIN(5, 18),	/* AVB1_AVTP_MATCH */
4210 		[19] = RCAR_GP_PIN(5, 19),	/* AVB1_AVTP_CAPTURE */
4211 		[20] = RCAR_GP_PIN(5, 20),	/* AVB1_AVTP_PPS */
4212 		[21] = SH_PFC_PIN_NONE,
4213 		[22] = SH_PFC_PIN_NONE,
4214 		[23] = SH_PFC_PIN_NONE,
4215 		[24] = SH_PFC_PIN_NONE,
4216 		[25] = SH_PFC_PIN_NONE,
4217 		[26] = SH_PFC_PIN_NONE,
4218 		[27] = SH_PFC_PIN_NONE,
4219 		[28] = SH_PFC_PIN_NONE,
4220 		[29] = SH_PFC_PIN_NONE,
4221 		[30] = SH_PFC_PIN_NONE,
4222 		[31] = SH_PFC_PIN_NONE,
4223 	} },
4224 	{ PINMUX_BIAS_REG("PUEN6", 0xe60680c0, "PUD6", 0xe60680e0) {
4225 		[ 0] = RCAR_GP_PIN(6,  0),	/* AVB2_RX_CTL */
4226 		[ 1] = RCAR_GP_PIN(6,  1),	/* AVB2_RXC */
4227 		[ 2] = RCAR_GP_PIN(6,  2),	/* AVB2_RD0 */
4228 		[ 3] = RCAR_GP_PIN(6,  3),	/* AVB2_RD1 */
4229 		[ 4] = RCAR_GP_PIN(6,  4),	/* AVB2_RD2 */
4230 		[ 5] = RCAR_GP_PIN(6,  5),	/* AVB2_RD3 */
4231 		[ 6] = RCAR_GP_PIN(6,  6),	/* AVB2_TX_CTL */
4232 		[ 7] = RCAR_GP_PIN(6,  7),	/* AVB2_TXC */
4233 		[ 8] = RCAR_GP_PIN(6,  8),	/* AVB2_TD0 */
4234 		[ 9] = RCAR_GP_PIN(6,  9),	/* AVB2_TD1 */
4235 		[10] = RCAR_GP_PIN(6, 10),	/* AVB2_TD2 */
4236 		[11] = RCAR_GP_PIN(6, 11),	/* AVB2_TD3 */
4237 		[12] = RCAR_GP_PIN(6, 12),	/* AVB2_TXCREFCLK */
4238 		[13] = RCAR_GP_PIN(6, 13),	/* AVB2_MDIO */
4239 		[14] = RCAR_GP_PIN(6, 14),	/* AVB2_MDC */
4240 		[15] = RCAR_GP_PIN(6, 15),	/* AVB2_MAGIC */
4241 		[16] = RCAR_GP_PIN(6, 16),	/* AVB2_PHY_INT */
4242 		[17] = RCAR_GP_PIN(6, 17),	/* AVB2_LINK */
4243 		[18] = RCAR_GP_PIN(6, 18),	/* AVB2_AVTP_MATCH */
4244 		[19] = RCAR_GP_PIN(6, 19),	/* AVB2_AVTP_CAPTURE */
4245 		[20] = RCAR_GP_PIN(6, 20),	/* AVB2_AVTP_PPS */
4246 		[21] = SH_PFC_PIN_NONE,
4247 		[22] = SH_PFC_PIN_NONE,
4248 		[23] = SH_PFC_PIN_NONE,
4249 		[24] = SH_PFC_PIN_NONE,
4250 		[25] = SH_PFC_PIN_NONE,
4251 		[26] = SH_PFC_PIN_NONE,
4252 		[27] = SH_PFC_PIN_NONE,
4253 		[28] = SH_PFC_PIN_NONE,
4254 		[29] = SH_PFC_PIN_NONE,
4255 		[30] = SH_PFC_PIN_NONE,
4256 		[31] = SH_PFC_PIN_NONE,
4257 	} },
4258 	{ PINMUX_BIAS_REG("PUEN7", 0xe60688c0, "PUD7", 0xe60688e0) {
4259 		[ 0] = RCAR_GP_PIN(7,  0),	/* AVB3_RX_CTL */
4260 		[ 1] = RCAR_GP_PIN(7,  1),	/* AVB3_RXC */
4261 		[ 2] = RCAR_GP_PIN(7,  2),	/* AVB3_RD0 */
4262 		[ 3] = RCAR_GP_PIN(7,  3),	/* AVB3_RD1 */
4263 		[ 4] = RCAR_GP_PIN(7,  4),	/* AVB3_RD2 */
4264 		[ 5] = RCAR_GP_PIN(7,  5),	/* AVB3_RD3 */
4265 		[ 6] = RCAR_GP_PIN(7,  6),	/* AVB3_TX_CTL */
4266 		[ 7] = RCAR_GP_PIN(7,  7),	/* AVB3_TXC */
4267 		[ 8] = RCAR_GP_PIN(7,  8),	/* AVB3_TD0 */
4268 		[ 9] = RCAR_GP_PIN(7,  9),	/* AVB3_TD1 */
4269 		[10] = RCAR_GP_PIN(7, 10),	/* AVB3_TD2 */
4270 		[11] = RCAR_GP_PIN(7, 11),	/* AVB3_TD3 */
4271 		[12] = RCAR_GP_PIN(7, 12),	/* AVB3_TXCREFCLK */
4272 		[13] = RCAR_GP_PIN(7, 13),	/* AVB3_MDIO */
4273 		[14] = RCAR_GP_PIN(7, 14),	/* AVB3_MDC */
4274 		[15] = RCAR_GP_PIN(7, 15),	/* AVB3_MAGIC */
4275 		[16] = RCAR_GP_PIN(7, 16),	/* AVB3_PHY_INT */
4276 		[17] = RCAR_GP_PIN(7, 17),	/* AVB3_LINK */
4277 		[18] = RCAR_GP_PIN(7, 18),	/* AVB3_AVTP_MATCH */
4278 		[19] = RCAR_GP_PIN(7, 19),	/* AVB3_AVTP_CAPTURE */
4279 		[20] = RCAR_GP_PIN(7, 20),	/* AVB3_AVTP_PPS */
4280 		[21] = SH_PFC_PIN_NONE,
4281 		[22] = SH_PFC_PIN_NONE,
4282 		[23] = SH_PFC_PIN_NONE,
4283 		[24] = SH_PFC_PIN_NONE,
4284 		[25] = SH_PFC_PIN_NONE,
4285 		[26] = SH_PFC_PIN_NONE,
4286 		[27] = SH_PFC_PIN_NONE,
4287 		[28] = SH_PFC_PIN_NONE,
4288 		[29] = SH_PFC_PIN_NONE,
4289 		[30] = SH_PFC_PIN_NONE,
4290 		[31] = SH_PFC_PIN_NONE,
4291 	} },
4292 	{ PINMUX_BIAS_REG("PUEN8", 0xe60690c0, "PUD8", 0xe60690e0) {
4293 		[ 0] = RCAR_GP_PIN(8,  0),	/* AVB4_RX_CTL */
4294 		[ 1] = RCAR_GP_PIN(8,  1),	/* AVB4_RXC */
4295 		[ 2] = RCAR_GP_PIN(8,  2),	/* AVB4_RD0 */
4296 		[ 3] = RCAR_GP_PIN(8,  3),	/* AVB4_RD1 */
4297 		[ 4] = RCAR_GP_PIN(8,  4),	/* AVB4_RD2 */
4298 		[ 5] = RCAR_GP_PIN(8,  5),	/* AVB4_RD3 */
4299 		[ 6] = RCAR_GP_PIN(8,  6),	/* AVB4_TX_CTL */
4300 		[ 7] = RCAR_GP_PIN(8,  7),	/* AVB4_TXC */
4301 		[ 8] = RCAR_GP_PIN(8,  8),	/* AVB4_TD0 */
4302 		[ 9] = RCAR_GP_PIN(8,  9),	/* AVB4_TD1 */
4303 		[10] = RCAR_GP_PIN(8, 10),	/* AVB4_TD2 */
4304 		[11] = RCAR_GP_PIN(8, 11),	/* AVB4_TD3 */
4305 		[12] = RCAR_GP_PIN(8, 12),	/* AVB4_TXCREFCLK */
4306 		[13] = RCAR_GP_PIN(8, 13),	/* AVB4_MDIO */
4307 		[14] = RCAR_GP_PIN(8, 14),	/* AVB4_MDC */
4308 		[15] = RCAR_GP_PIN(8, 15),	/* AVB4_MAGIC */
4309 		[16] = RCAR_GP_PIN(8, 16),	/* AVB4_PHY_INT */
4310 		[17] = RCAR_GP_PIN(8, 17),	/* AVB4_LINK */
4311 		[18] = RCAR_GP_PIN(8, 18),	/* AVB4_AVTP_MATCH */
4312 		[19] = RCAR_GP_PIN(8, 19),	/* AVB4_AVTP_CAPTURE */
4313 		[20] = RCAR_GP_PIN(8, 20),	/* AVB4_AVTP_PPS */
4314 		[21] = SH_PFC_PIN_NONE,
4315 		[22] = SH_PFC_PIN_NONE,
4316 		[23] = SH_PFC_PIN_NONE,
4317 		[24] = SH_PFC_PIN_NONE,
4318 		[25] = SH_PFC_PIN_NONE,
4319 		[26] = SH_PFC_PIN_NONE,
4320 		[27] = SH_PFC_PIN_NONE,
4321 		[28] = SH_PFC_PIN_NONE,
4322 		[29] = SH_PFC_PIN_NONE,
4323 		[30] = SH_PFC_PIN_NONE,
4324 		[31] = SH_PFC_PIN_NONE,
4325 	} },
4326 	{ PINMUX_BIAS_REG("PUEN9", 0xe60698c0, "PUD9", 0xe60698e0) {
4327 		[ 0] = RCAR_GP_PIN(9,  0),	/* AVB5_RX_CTL */
4328 		[ 1] = RCAR_GP_PIN(9,  1),	/* AVB5_RXC */
4329 		[ 2] = RCAR_GP_PIN(9,  2),	/* AVB5_RD0 */
4330 		[ 3] = RCAR_GP_PIN(9,  3),	/* AVB5_RD1 */
4331 		[ 4] = RCAR_GP_PIN(9,  4),	/* AVB5_RD2 */
4332 		[ 5] = RCAR_GP_PIN(9,  5),	/* AVB5_RD3 */
4333 		[ 6] = RCAR_GP_PIN(9,  6),	/* AVB5_TX_CTL */
4334 		[ 7] = RCAR_GP_PIN(9,  7),	/* AVB5_TXC */
4335 		[ 8] = RCAR_GP_PIN(9,  8),	/* AVB5_TD0 */
4336 		[ 9] = RCAR_GP_PIN(9,  9),	/* AVB5_TD1 */
4337 		[10] = RCAR_GP_PIN(9, 10),	/* AVB5_TD2 */
4338 		[11] = RCAR_GP_PIN(9, 11),	/* AVB5_TD3 */
4339 		[12] = RCAR_GP_PIN(9, 12),	/* AVB5_TXCREFCLK */
4340 		[13] = RCAR_GP_PIN(9, 13),	/* AVB5_MDIO */
4341 		[14] = RCAR_GP_PIN(9, 14),	/* AVB5_MDC */
4342 		[15] = RCAR_GP_PIN(9, 15),	/* AVB5_MAGIC */
4343 		[16] = RCAR_GP_PIN(9, 16),	/* AVB5_PHY_INT */
4344 		[17] = RCAR_GP_PIN(9, 17),	/* AVB5_LINK */
4345 		[18] = RCAR_GP_PIN(9, 18),	/* AVB5_AVTP_MATCH */
4346 		[19] = RCAR_GP_PIN(9, 19),	/* AVB5_AVTP_CAPTURE */
4347 		[20] = RCAR_GP_PIN(9, 20),	/* AVB5_AVTP_PPS */
4348 		[21] = SH_PFC_PIN_NONE,
4349 		[22] = SH_PFC_PIN_NONE,
4350 		[23] = SH_PFC_PIN_NONE,
4351 		[24] = SH_PFC_PIN_NONE,
4352 		[25] = SH_PFC_PIN_NONE,
4353 		[26] = SH_PFC_PIN_NONE,
4354 		[27] = SH_PFC_PIN_NONE,
4355 		[28] = SH_PFC_PIN_NONE,
4356 		[29] = SH_PFC_PIN_NONE,
4357 		[30] = SH_PFC_PIN_NONE,
4358 		[31] = SH_PFC_PIN_NONE,
4359 	} },
4360 	{ /* sentinel */ },
4361 };
4362 
4363 static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = {
4364 	.pin_to_pocctrl = r8a779a0_pin_to_pocctrl,
4365 	.get_bias = rcar_pinmux_get_bias,
4366 	.set_bias = rcar_pinmux_set_bias,
4367 };
4368 
4369 const struct sh_pfc_soc_info r8a779a0_pinmux_info = {
4370 	.name = "r8a779a0_pfc",
4371 	.ops = &r8a779a0_pfc_ops,
4372 	.unlock_reg = 0x1ff,	/* PMMRn mask */
4373 
4374 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4375 
4376 	.pins = pinmux_pins,
4377 	.nr_pins = ARRAY_SIZE(pinmux_pins),
4378 	.groups = pinmux_groups,
4379 	.nr_groups = ARRAY_SIZE(pinmux_groups),
4380 	.functions = pinmux_functions,
4381 	.nr_functions = ARRAY_SIZE(pinmux_functions),
4382 
4383 	.cfg_regs = pinmux_config_regs,
4384 	.drive_regs = pinmux_drive_regs,
4385 	.bias_regs = pinmux_bias_regs,
4386 	.ioctrl_regs = pinmux_ioctrl_regs,
4387 
4388 	.pinmux_data = pinmux_data,
4389 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
4390 };
4391