| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | hdp_v4_0.c | 46 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in hdp_v4_0_flush_hdp()
58 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in hdp_v4_0_invalidate_hdp()
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| D | hdp_v5_0.c | 37 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in hdp_v5_0_flush_hdp()
46 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in hdp_v5_0_invalidate_hdp()
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| D | gmc_v11_0.c | 384 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v11_0_emit_flush_gpu_tlb()
388 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v11_0_emit_flush_gpu_tlb()
404 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v11_0_emit_flush_gpu_tlb()
425 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v11_0_emit_pasid_mapping()
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| D | hdp_v6_0.c | 37 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in hdp_v6_0_flush_hdp()
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| D | hdp_v5_2.c | 38 amdgpu_ring_emit_wreg(ring, in hdp_v5_2_flush_hdp()
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| D | gmc_v10_0.c | 493 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v10_0_emit_flush_gpu_tlb()
497 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v10_0_emit_flush_gpu_tlb()
513 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v10_0_emit_flush_gpu_tlb()
534 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v10_0_emit_pasid_mapping()
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| D | gmc_v9_0.c | 993 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v9_0_emit_flush_gpu_tlb()
997 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v9_0_emit_flush_gpu_tlb()
1013 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v9_0_emit_flush_gpu_tlb()
1034 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v9_0_emit_pasid_mapping()
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| D | gmc_v6_0.c | 371 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v6_0_emit_flush_gpu_tlb()
374 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v6_0_emit_flush_gpu_tlb()
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| D | gmc_v7_0.c | 491 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v7_0_emit_flush_gpu_tlb()
494 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v7_0_emit_flush_gpu_tlb()
502 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v7_0_emit_pasid_mapping()
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| D | gmc_v8_0.c | 690 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v8_0_emit_flush_gpu_tlb()
693 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v8_0_emit_flush_gpu_tlb()
701 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v8_0_emit_pasid_mapping()
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| D | amdgpu_ring.c | 390 amdgpu_ring_emit_wreg(ring, reg0, ref); in amdgpu_ring_emit_reg_write_reg_wait_helper()
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| D | amdgpu_ring.h | 300 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) macro
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| D | cik.c | 1895 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in cik_flush_hdp()
1906 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in cik_invalidate_hdp()
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| D | vi.c | 1349 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in vi_flush_hdp()
1360 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in vi_invalidate_hdp()
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| D | si.c | 1489 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in si_flush_hdp()
1500 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in si_invalidate_hdp()
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| D | amdgpu_gfx.c | 826 amdgpu_ring_emit_wreg(ring, reg, v); in amdgpu_kiq_wreg()
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| D | sdma_v6_0.c | 1228 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v6_0_ring_emit_reg_write_reg_wait()
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| D | sdma_v5_2.c | 1231 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v5_2_ring_emit_reg_write_reg_wait()
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| D | sdma_v5_0.c | 1360 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v5_0_ring_emit_reg_write_reg_wait()
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| D | gfx_v9_0.c | 6615 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_0_emit_wave_limit_cs()
6630 amdgpu_ring_emit_wreg(ring, in gfx_v9_0_emit_wave_limit()
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| D | gfx_v8_0.c | 6868 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v8_0_emit_wave_limit_cs()
6884 amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val); in gfx_v8_0_emit_wave_limit()
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