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Searched refs:_shift (Results 1 – 25 of 190) sorted by relevance

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/linux-6.1.9/drivers/iio/dac/
Dad5686.c191 #define AD5868_CHANNEL(chan, addr, bits, _shift) { \ argument
203 .shift = (_shift), \
208 #define DECLARE_AD5693_CHANNELS(name, bits, _shift) \ argument
210 AD5868_CHANNEL(0, 0, bits, _shift), \
213 #define DECLARE_AD5338_CHANNELS(name, bits, _shift) \ argument
215 AD5868_CHANNEL(0, 1, bits, _shift), \
216 AD5868_CHANNEL(1, 8, bits, _shift), \
219 #define DECLARE_AD5686_CHANNELS(name, bits, _shift) \ argument
221 AD5868_CHANNEL(0, 1, bits, _shift), \
222 AD5868_CHANNEL(1, 2, bits, _shift), \
[all …]
/linux-6.1.9/drivers/clk/sunxi-ng/
Dccu_mux.h32 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ argument
34 .shift = _shift, \
39 #define _SUNXI_CCU_MUX(_shift, _width) \ argument
40 _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
50 _reg, _shift, _width, _gate, \ argument
54 .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
65 _shift, _width, _gate, _flags) \ argument
67 _reg, _shift, _width, _gate, \
70 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
73 _reg, _shift, _width, 0, _flags)
[all …]
Dccu_div.h43 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument
45 .shift = _shift, \
51 #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \ argument
52 _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
54 #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \ argument
56 .shift = _shift, \
63 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ argument
64 _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
66 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument
67 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
[all …]
Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
22 .shift = _shift, \
26 #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \ argument
27 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0)
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
32 #define _SUNXI_CCU_MULT(_shift, _width) \ argument
33 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, 1, 0)
/linux-6.1.9/drivers/clk/mediatek/
Dclk-mt8195-infra_ao.c44 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
45 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
48 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
49 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
51 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
52 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
55 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
56 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
58 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
59 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
[all …]
Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
61 GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
Dclk-mt8186-infra_ao.c38 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
39 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
42 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
43 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
45 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
46 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
49 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
50 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
52 #define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
53 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
[all …]
Dclk-mt8186-vdec.c39 #define GATE_VDEC0(_id, _name, _parent, _shift) \ argument
40 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
42 #define GATE_VDEC1(_id, _name, _parent, _shift) \ argument
43 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
45 #define GATE_VDEC2(_id, _name, _parent, _shift) \ argument
46 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
48 #define GATE_VDEC3(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &vdec3_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
Dclk-mt8195-vdo1.c43 #define GATE_VDO1_0(_id, _name, _parent, _shift) \ argument
44 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
46 #define GATE_VDO1_1(_id, _name, _parent, _shift) \ argument
47 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
49 #define GATE_VDO1_2(_id, _name, _parent, _shift) \ argument
50 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
52 #define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
53 GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \
56 #define GATE_VDO1_3(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
[all …]
Dclk-mtk.h88 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
93 .mux_shift = _shift, \
108 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
111 _shift, _width, _gate, _flags, 0)
117 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
118 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
121 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
123 _shift, _width, CLK_SET_RATE_PARENT)
125 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
129 .mux_shift = _shift, \
[all …]
Dclk-mux.h41 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
49 .mux_shift = _shift, \
63 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
66 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
71 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
74 _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
79 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
82 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
Dclk-mt8192-vdec.c33 #define GATE_VDEC0(_id, _name, _parent, _shift) \ argument
34 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
36 #define GATE_VDEC1(_id, _name, _parent, _shift) \ argument
37 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
39 #define GATE_VDEC2(_id, _name, _parent, _shift) \ argument
40 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
Dclk-mt8195-vdec.c31 #define GATE_VDEC0(_id, _name, _parent, _shift) \ argument
32 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
34 #define GATE_VDEC1(_id, _name, _parent, _shift) \ argument
35 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
37 #define GATE_VDEC2(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
Dclk-mt8195-vdo0.c31 #define GATE_VDO0_0(_id, _name, _parent, _shift) \ argument
32 GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
34 #define GATE_VDO0_1(_id, _name, _parent, _shift) \ argument
35 GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VDO0_2(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
40 #define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
41 GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \
Dclk-mt2701-aud.c18 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
23 .shift = _shift, \
27 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
32 .shift = _shift, \
36 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
41 .shift = _shift, \
45 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
50 .shift = _shift, \
Dclk-mt7622-aud.c19 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
24 .shift = _shift, \
28 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
33 .shift = _shift, \
37 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
42 .shift = _shift, \
46 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
51 .shift = _shift, \
Dclk-mt8195-vpp0.c31 #define GATE_VPP0_0(_id, _name, _parent, _shift) \ argument
32 GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
34 #define GATE_VPP0_1(_id, _name, _parent, _shift) \ argument
35 GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VPP0_2(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
Dclk-mt8192-mm.c32 #define GATE_MM0(_id, _name, _parent, _shift) \ argument
33 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
35 #define GATE_MM1(_id, _name, _parent, _shift) \ argument
36 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
38 #define GATE_MM2(_id, _name, _parent, _shift) \ argument
39 GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
Dclk-mt8167.c658 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
663 .div_shift = _shift, \
688 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ argument
693 .div_shift = _shift, \
739 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
744 .shift = _shift, \
748 #define GATE_TOP0_I(_id, _name, _parent, _shift) { \ argument
753 .shift = _shift, \
757 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
762 .shift = _shift, \
[all …]
Dclk-mt8192.c726 #define GATE_APMIXED(_id, _name, _parent, _shift) \ argument
727 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
769 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
770 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
772 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
773 GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \
776 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
777 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
779 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
780 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
[all …]
Dclk-mt8192-aud.c33 #define GATE_AUD0(_id, _name, _parent, _shift) \ argument
34 GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
36 #define GATE_AUD1(_id, _name, _parent, _shift) \ argument
37 GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
39 #define GATE_AUD2(_id, _name, _parent, _shift) \ argument
40 GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
/linux-6.1.9/drivers/clk/sprd/
Dmux.h32 #define _SPRD_MUX_CLK(_shift, _width, _table) \ argument
34 .shift = _shift, \
40 _reg, _shift, _width, _flags, _fn) \ argument
42 .mux = _SPRD_MUX_CLK(_shift, _width, _table), \
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
58 _shift, _width, _flags) \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
[all …]
Ddiv.h27 #define _SPRD_DIV_CLK(_shift, _width) \ argument
29 .shift = _shift, \
39 _shift, _width, _flags, _fn) \ argument
41 .div = _SPRD_DIV_CLK(_shift, _width), \
51 _shift, _width, _flags) \ argument
53 _shift, _width, _flags, CLK_HW_INIT)
56 _shift, _width, _flags) \ argument
58 _shift, _width, _flags, CLK_HW_INIT_HW)
/linux-6.1.9/drivers/clk/actions/
Dowl-pll.h41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
47 .shift = _shift, \
56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
85 _shift, _width, _min_mul, _max_mul, _delay, _table, \ argument
88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
/linux-6.1.9/drivers/net/ethernet/mellanox/mlxsw/
Dcore_acl_flex_keys.h52 #define MLXSW_AFK_ELEMENT_INFO(_type, _element, _offset, _shift, _size) \ argument
58 .shift = _shift, \
64 #define MLXSW_AFK_ELEMENT_INFO_U32(_element, _offset, _shift, _size) \ argument
66 _element, _offset, _shift, _size)
85 _shift, _size, _u32_key_diff, _avoid_size_check) \ argument
91 .shift = _shift, \
99 #define MLXSW_AFK_ELEMENT_INST_U32(_element, _offset, _shift, _size) \ argument
101 _element, _offset, _shift, _size, 0, false)
104 _shift, _size, _key_diff, \ argument
107 _element, _offset, _shift, _size, \

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