| /linux-6.1.9/drivers/clk/stm32/ |
| D | clk-stm32-core.h | 166 #define STM32_CLOCK_CFG(_binding, _clk, _sec_id, _struct, _register)\ argument
170 .clock_cfg = (_struct) {_clk},\
174 #define STM32_MUX_CFG(_binding, _clk, _sec_id)\ argument
175 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_mux *,\
178 #define STM32_GATE_CFG(_binding, _clk, _sec_id)\ argument
179 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_gate *,\
182 #define STM32_DIV_CFG(_binding, _clk, _sec_id)\ argument
183 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_div *,\
186 #define STM32_COMPOSITE_CFG(_binding, _clk, _sec_id)\ argument
187 STM32_CLOCK_CFG(_binding, &(_clk), _sec_id, struct clk_stm32_composite *,\
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| /linux-6.1.9/include/linux/ |
| D | sh_clk.h | 200 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } argument
201 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } argument
202 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } argument
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| /linux-6.1.9/arch/arm/mach-omap2/ |
| D | omap_hwmod.c | 635 } else if (oh->_clk) { in _get_clkdm()
636 if (!omap2_clk_is_hw_omap(__clk_get_hw(oh->_clk))) in _get_clkdm()
638 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); in _get_clkdm()
835 oh->_clk = clk; in _init_main_clk()
841 oh->_clk = clk_get(NULL, oh->main_clk); in _init_main_clk()
844 if (IS_ERR(oh->_clk)) { in _init_main_clk()
857 clk_prepare(oh->_clk); in _init_main_clk()
890 os->_clk = c; in _init_interface_clks()
899 clk_prepare(os->_clk); in _init_interface_clks()
927 oc->_clk = c; in _init_opt_clks()
[all …]
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| D | omap_hwmod.h | 181 struct clk *_clk; member
244 struct clk *_clk; member
585 struct clk *_clk; member
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| D | display.c | 383 clk_prepare_enable(oc->_clk); in omap_dss_reset()
409 clk_disable_unprepare(oc->_clk); in omap_dss_reset()
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| /linux-6.1.9/Documentation/devicetree/bindings/media/ |
| D | cdns,csi2rx.txt | 14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
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| D | cdns,csi2tx.txt | 15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
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| /linux-6.1.9/drivers/ufs/host/ |
| D | ufs-exynos.c | 497 unsigned long clk = 0, _clk, clk_period; in exynos_ufs_calc_pwm_clk_div() local
502 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div); in exynos_ufs_calc_pwm_clk_div()
503 if (_clk >= pwm_min && _clk <= pwm_max) { in exynos_ufs_calc_pwm_clk_div()
504 if (_clk > clk) { in exynos_ufs_calc_pwm_clk_div()
506 clk = _clk; in exynos_ufs_calc_pwm_clk_div()
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| /linux-6.1.9/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gm20b.c | 852 struct gm20b_clk *_clk = gm20b_clk(base); in gm20b_clk_init() local
856 _clk->uv = nvkm_volt_get(volt); in gm20b_clk_init()
859 ret = gm20b_clk_init_dvfs(_clk); in gm20b_clk_init()
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| /linux-6.1.9/drivers/clk/renesas/ |
| D | r9a06g032-clocks.c | 62 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \ argument
63 { .gate = _clk, .reset = _rst, \
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