1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Xilinx Zynq MPSoC Firmware layer
4 *
5 * Copyright (C) 2014-2021 Xilinx
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
11 */
12
13 #ifndef __FIRMWARE_ZYNQMP_H__
14 #define __FIRMWARE_ZYNQMP_H__
15
16 #include <linux/err.h>
17
18 #define ZYNQMP_PM_VERSION_MAJOR 1
19 #define ZYNQMP_PM_VERSION_MINOR 0
20
21 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
22 ZYNQMP_PM_VERSION_MINOR)
23
24 #define ZYNQMP_TZ_VERSION_MAJOR 1
25 #define ZYNQMP_TZ_VERSION_MINOR 0
26
27 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
28 ZYNQMP_TZ_VERSION_MINOR)
29
30 /* SMC SIP service Call Function Identifier Prefix */
31 #define PM_SIP_SVC 0xC2000000
32
33 /* PM API versions */
34 #define PM_API_VERSION_2 2
35
36 /* ATF only commands */
37 #define TF_A_PM_REGISTER_SGI 0xa04
38 #define PM_GET_TRUSTZONE_VERSION 0xa03
39 #define PM_SET_SUSPEND_MODE 0xa02
40 #define GET_CALLBACK_DATA 0xa01
41
42 /* Number of 32bits values in payload */
43 #define PAYLOAD_ARG_CNT 4U
44
45 /* Number of arguments for a callback */
46 #define CB_ARG_CNT 4
47
48 /* Payload size (consists of callback API ID + arguments) */
49 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
50
51 #define ZYNQMP_PM_MAX_QOS 100U
52
53 #define GSS_NUM_REGS (4)
54
55 /* Node capabilities */
56 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
57 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
58 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
59 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
60
61 /* Loader commands */
62 #define PM_LOAD_PDI 0x701
63 #define PDI_SRC_DDR 0xF
64
65 /*
66 * Firmware FPGA Manager flags
67 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
68 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
69 */
70 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
71 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
72
73 /*
74 * Node IDs for the Error Events.
75 */
76 #define EVENT_ERROR_PMC_ERR1 (0x28100000U)
77 #define EVENT_ERROR_PMC_ERR2 (0x28104000U)
78 #define EVENT_ERROR_PSM_ERR1 (0x28108000U)
79 #define EVENT_ERROR_PSM_ERR2 (0x2810C000U)
80
81 enum pm_api_cb_id {
82 PM_INIT_SUSPEND_CB = 30,
83 PM_ACKNOWLEDGE_CB = 31,
84 PM_NOTIFY_CB = 32,
85 };
86
87 enum pm_api_id {
88 PM_GET_API_VERSION = 1,
89 PM_REGISTER_NOTIFIER = 5,
90 PM_SYSTEM_SHUTDOWN = 12,
91 PM_REQUEST_NODE = 13,
92 PM_RELEASE_NODE = 14,
93 PM_SET_REQUIREMENT = 15,
94 PM_RESET_ASSERT = 17,
95 PM_RESET_GET_STATUS = 18,
96 PM_MMIO_WRITE = 19,
97 PM_MMIO_READ = 20,
98 PM_PM_INIT_FINALIZE = 21,
99 PM_FPGA_LOAD = 22,
100 PM_FPGA_GET_STATUS = 23,
101 PM_GET_CHIPID = 24,
102 PM_SECURE_SHA = 26,
103 PM_PINCTRL_REQUEST = 28,
104 PM_PINCTRL_RELEASE = 29,
105 PM_PINCTRL_GET_FUNCTION = 30,
106 PM_PINCTRL_SET_FUNCTION = 31,
107 PM_PINCTRL_CONFIG_PARAM_GET = 32,
108 PM_PINCTRL_CONFIG_PARAM_SET = 33,
109 PM_IOCTL = 34,
110 PM_QUERY_DATA = 35,
111 PM_CLOCK_ENABLE = 36,
112 PM_CLOCK_DISABLE = 37,
113 PM_CLOCK_GETSTATE = 38,
114 PM_CLOCK_SETDIVIDER = 39,
115 PM_CLOCK_GETDIVIDER = 40,
116 PM_CLOCK_SETRATE = 41,
117 PM_CLOCK_GETRATE = 42,
118 PM_CLOCK_SETPARENT = 43,
119 PM_CLOCK_GETPARENT = 44,
120 PM_SECURE_AES = 47,
121 PM_FEATURE_CHECK = 63,
122 };
123
124 /* PMU-FW return status codes */
125 enum pm_ret_status {
126 XST_PM_SUCCESS = 0,
127 XST_PM_NO_FEATURE = 19,
128 XST_PM_INTERNAL = 2000,
129 XST_PM_CONFLICT = 2001,
130 XST_PM_NO_ACCESS = 2002,
131 XST_PM_INVALID_NODE = 2003,
132 XST_PM_DOUBLE_REQ = 2004,
133 XST_PM_ABORT_SUSPEND = 2005,
134 XST_PM_MULT_USER = 2008,
135 };
136
137 enum pm_ioctl_id {
138 IOCTL_SD_DLL_RESET = 6,
139 IOCTL_SET_SD_TAPDELAY = 7,
140 IOCTL_SET_PLL_FRAC_MODE = 8,
141 IOCTL_GET_PLL_FRAC_MODE = 9,
142 IOCTL_SET_PLL_FRAC_DATA = 10,
143 IOCTL_GET_PLL_FRAC_DATA = 11,
144 IOCTL_WRITE_GGS = 12,
145 IOCTL_READ_GGS = 13,
146 IOCTL_WRITE_PGGS = 14,
147 IOCTL_READ_PGGS = 15,
148 /* Set healthy bit value */
149 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
150 IOCTL_OSPI_MUX_SELECT = 21,
151 /* Register SGI to ATF */
152 IOCTL_REGISTER_SGI = 25,
153 /* Runtime feature configuration */
154 IOCTL_SET_FEATURE_CONFIG = 26,
155 IOCTL_GET_FEATURE_CONFIG = 27,
156 /* Dynamic SD/GEM configuration */
157 IOCTL_SET_SD_CONFIG = 30,
158 IOCTL_SET_GEM_CONFIG = 31,
159 };
160
161 enum pm_query_id {
162 PM_QID_INVALID = 0,
163 PM_QID_CLOCK_GET_NAME = 1,
164 PM_QID_CLOCK_GET_TOPOLOGY = 2,
165 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
166 PM_QID_CLOCK_GET_PARENTS = 4,
167 PM_QID_CLOCK_GET_ATTRIBUTES = 5,
168 PM_QID_PINCTRL_GET_NUM_PINS = 6,
169 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
170 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
171 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
172 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
173 PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
174 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
175 PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
176 };
177
178 enum zynqmp_pm_reset_action {
179 PM_RESET_ACTION_RELEASE = 0,
180 PM_RESET_ACTION_ASSERT = 1,
181 PM_RESET_ACTION_PULSE = 2,
182 };
183
184 enum zynqmp_pm_reset {
185 ZYNQMP_PM_RESET_START = 1000,
186 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
187 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
188 ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
189 ZYNQMP_PM_RESET_DP = 1003,
190 ZYNQMP_PM_RESET_SWDT_CRF = 1004,
191 ZYNQMP_PM_RESET_AFI_FM5 = 1005,
192 ZYNQMP_PM_RESET_AFI_FM4 = 1006,
193 ZYNQMP_PM_RESET_AFI_FM3 = 1007,
194 ZYNQMP_PM_RESET_AFI_FM2 = 1008,
195 ZYNQMP_PM_RESET_AFI_FM1 = 1009,
196 ZYNQMP_PM_RESET_AFI_FM0 = 1010,
197 ZYNQMP_PM_RESET_GDMA = 1011,
198 ZYNQMP_PM_RESET_GPU_PP1 = 1012,
199 ZYNQMP_PM_RESET_GPU_PP0 = 1013,
200 ZYNQMP_PM_RESET_GPU = 1014,
201 ZYNQMP_PM_RESET_GT = 1015,
202 ZYNQMP_PM_RESET_SATA = 1016,
203 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
204 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
205 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
206 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
207 ZYNQMP_PM_RESET_APU_L2 = 1021,
208 ZYNQMP_PM_RESET_ACPU3 = 1022,
209 ZYNQMP_PM_RESET_ACPU2 = 1023,
210 ZYNQMP_PM_RESET_ACPU1 = 1024,
211 ZYNQMP_PM_RESET_ACPU0 = 1025,
212 ZYNQMP_PM_RESET_DDR = 1026,
213 ZYNQMP_PM_RESET_APM_FPD = 1027,
214 ZYNQMP_PM_RESET_SOFT = 1028,
215 ZYNQMP_PM_RESET_GEM0 = 1029,
216 ZYNQMP_PM_RESET_GEM1 = 1030,
217 ZYNQMP_PM_RESET_GEM2 = 1031,
218 ZYNQMP_PM_RESET_GEM3 = 1032,
219 ZYNQMP_PM_RESET_QSPI = 1033,
220 ZYNQMP_PM_RESET_UART0 = 1034,
221 ZYNQMP_PM_RESET_UART1 = 1035,
222 ZYNQMP_PM_RESET_SPI0 = 1036,
223 ZYNQMP_PM_RESET_SPI1 = 1037,
224 ZYNQMP_PM_RESET_SDIO0 = 1038,
225 ZYNQMP_PM_RESET_SDIO1 = 1039,
226 ZYNQMP_PM_RESET_CAN0 = 1040,
227 ZYNQMP_PM_RESET_CAN1 = 1041,
228 ZYNQMP_PM_RESET_I2C0 = 1042,
229 ZYNQMP_PM_RESET_I2C1 = 1043,
230 ZYNQMP_PM_RESET_TTC0 = 1044,
231 ZYNQMP_PM_RESET_TTC1 = 1045,
232 ZYNQMP_PM_RESET_TTC2 = 1046,
233 ZYNQMP_PM_RESET_TTC3 = 1047,
234 ZYNQMP_PM_RESET_SWDT_CRL = 1048,
235 ZYNQMP_PM_RESET_NAND = 1049,
236 ZYNQMP_PM_RESET_ADMA = 1050,
237 ZYNQMP_PM_RESET_GPIO = 1051,
238 ZYNQMP_PM_RESET_IOU_CC = 1052,
239 ZYNQMP_PM_RESET_TIMESTAMP = 1053,
240 ZYNQMP_PM_RESET_RPU_R50 = 1054,
241 ZYNQMP_PM_RESET_RPU_R51 = 1055,
242 ZYNQMP_PM_RESET_RPU_AMBA = 1056,
243 ZYNQMP_PM_RESET_OCM = 1057,
244 ZYNQMP_PM_RESET_RPU_PGE = 1058,
245 ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
246 ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
247 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
248 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
249 ZYNQMP_PM_RESET_USB0_APB = 1063,
250 ZYNQMP_PM_RESET_USB1_APB = 1064,
251 ZYNQMP_PM_RESET_IPI = 1065,
252 ZYNQMP_PM_RESET_APM_LPD = 1066,
253 ZYNQMP_PM_RESET_RTC = 1067,
254 ZYNQMP_PM_RESET_SYSMON = 1068,
255 ZYNQMP_PM_RESET_AFI_FM6 = 1069,
256 ZYNQMP_PM_RESET_LPD_SWDT = 1070,
257 ZYNQMP_PM_RESET_FPD = 1071,
258 ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
259 ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
260 ZYNQMP_PM_RESET_DBG_LPD = 1074,
261 ZYNQMP_PM_RESET_DBG_FPD = 1075,
262 ZYNQMP_PM_RESET_APLL = 1076,
263 ZYNQMP_PM_RESET_DPLL = 1077,
264 ZYNQMP_PM_RESET_VPLL = 1078,
265 ZYNQMP_PM_RESET_IOPLL = 1079,
266 ZYNQMP_PM_RESET_RPLL = 1080,
267 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
268 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
269 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
270 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
271 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
272 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
273 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
274 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
275 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
276 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
277 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
278 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
279 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
280 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
281 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
282 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
283 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
284 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
285 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
286 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
287 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
288 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
289 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
290 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
291 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
292 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
293 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
294 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
295 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
296 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
297 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
298 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
299 ZYNQMP_PM_RESET_RPU_LS = 1113,
300 ZYNQMP_PM_RESET_PS_ONLY = 1114,
301 ZYNQMP_PM_RESET_PL = 1115,
302 ZYNQMP_PM_RESET_PS_PL0 = 1116,
303 ZYNQMP_PM_RESET_PS_PL1 = 1117,
304 ZYNQMP_PM_RESET_PS_PL2 = 1118,
305 ZYNQMP_PM_RESET_PS_PL3 = 1119,
306 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
307 };
308
309 enum zynqmp_pm_suspend_reason {
310 SUSPEND_POWER_REQUEST = 201,
311 SUSPEND_ALERT = 202,
312 SUSPEND_SYSTEM_SHUTDOWN = 203,
313 };
314
315 enum zynqmp_pm_request_ack {
316 ZYNQMP_PM_REQUEST_ACK_NO = 1,
317 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
318 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
319 };
320
321 enum pm_node_id {
322 NODE_SD_0 = 39,
323 NODE_SD_1 = 40,
324 };
325
326 enum tap_delay_type {
327 PM_TAPDELAY_INPUT = 0,
328 PM_TAPDELAY_OUTPUT = 1,
329 };
330
331 enum dll_reset_type {
332 PM_DLL_RESET_ASSERT = 0,
333 PM_DLL_RESET_RELEASE = 1,
334 PM_DLL_RESET_PULSE = 2,
335 };
336
337 enum pm_pinctrl_config_param {
338 PM_PINCTRL_CONFIG_SLEW_RATE = 0,
339 PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
340 PM_PINCTRL_CONFIG_PULL_CTRL = 2,
341 PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
342 PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
343 PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
344 PM_PINCTRL_CONFIG_TRI_STATE = 6,
345 PM_PINCTRL_CONFIG_MAX = 7,
346 };
347
348 enum pm_pinctrl_slew_rate {
349 PM_PINCTRL_SLEW_RATE_FAST = 0,
350 PM_PINCTRL_SLEW_RATE_SLOW = 1,
351 };
352
353 enum pm_pinctrl_bias_status {
354 PM_PINCTRL_BIAS_DISABLE = 0,
355 PM_PINCTRL_BIAS_ENABLE = 1,
356 };
357
358 enum pm_pinctrl_pull_ctrl {
359 PM_PINCTRL_BIAS_PULL_DOWN = 0,
360 PM_PINCTRL_BIAS_PULL_UP = 1,
361 };
362
363 enum pm_pinctrl_schmitt_cmos {
364 PM_PINCTRL_INPUT_TYPE_CMOS = 0,
365 PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
366 };
367
368 enum pm_pinctrl_drive_strength {
369 PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
370 PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
371 PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
372 PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
373 };
374
375 enum pm_pinctrl_tri_state {
376 PM_PINCTRL_TRI_STATE_DISABLE = 0,
377 PM_PINCTRL_TRI_STATE_ENABLE = 1,
378 };
379
380 enum zynqmp_pm_shutdown_type {
381 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
382 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
383 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
384 };
385
386 enum zynqmp_pm_shutdown_subtype {
387 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
388 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
389 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
390 };
391
392 enum ospi_mux_select_type {
393 PM_OSPI_MUX_SEL_DMA = 0,
394 PM_OSPI_MUX_SEL_LINEAR = 1,
395 };
396
397 enum pm_feature_config_id {
398 PM_FEATURE_INVALID = 0,
399 PM_FEATURE_OVERTEMP_STATUS = 1,
400 PM_FEATURE_OVERTEMP_VALUE = 2,
401 PM_FEATURE_EXTWDT_STATUS = 3,
402 PM_FEATURE_EXTWDT_VALUE = 4,
403 };
404
405 /**
406 * enum pm_sd_config_type - PM SD configuration.
407 * @SD_CONFIG_EMMC_SEL: To set SD_EMMC_SEL in CTRL_REG_SD and SD_SLOTTYPE
408 * @SD_CONFIG_BASECLK: To set SD_BASECLK in SD_CONFIG_REG1
409 * @SD_CONFIG_8BIT: To set SD_8BIT in SD_CONFIG_REG2
410 * @SD_CONFIG_FIXED: To set fixed config registers
411 */
412 enum pm_sd_config_type {
413 SD_CONFIG_EMMC_SEL = 1,
414 SD_CONFIG_BASECLK = 2,
415 SD_CONFIG_8BIT = 3,
416 SD_CONFIG_FIXED = 4,
417 };
418
419 /**
420 * enum pm_gem_config_type - PM GEM configuration.
421 * @GEM_CONFIG_SGMII_MODE: To set GEM_SGMII_MODE in GEM_CLK_CTRL register
422 * @GEM_CONFIG_FIXED: To set fixed config registers
423 */
424 enum pm_gem_config_type {
425 GEM_CONFIG_SGMII_MODE = 1,
426 GEM_CONFIG_FIXED = 2,
427 };
428
429 /**
430 * struct zynqmp_pm_query_data - PM query data
431 * @qid: query ID
432 * @arg1: Argument 1 of query data
433 * @arg2: Argument 2 of query data
434 * @arg3: Argument 3 of query data
435 */
436 struct zynqmp_pm_query_data {
437 u32 qid;
438 u32 arg1;
439 u32 arg2;
440 u32 arg3;
441 };
442
443 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
444 u32 arg2, u32 arg3, u32 *ret_payload);
445
446 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
447 int zynqmp_pm_get_api_version(u32 *version);
448 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
449 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
450 int zynqmp_pm_clock_enable(u32 clock_id);
451 int zynqmp_pm_clock_disable(u32 clock_id);
452 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
453 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
454 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
455 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
456 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
457 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
458 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
459 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
460 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
461 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
462 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
463 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
464 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
465 int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select);
466 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
467 const enum zynqmp_pm_reset_action assert_flag);
468 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
469 unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode);
470 int zynqmp_pm_bootmode_write(u32 ps_mode);
471 int zynqmp_pm_init_finalize(void);
472 int zynqmp_pm_set_suspend_mode(u32 mode);
473 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
474 const u32 qos, const enum zynqmp_pm_request_ack ack);
475 int zynqmp_pm_release_node(const u32 node);
476 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
477 const u32 qos,
478 const enum zynqmp_pm_request_ack ack);
479 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
480 int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
481 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
482 int zynqmp_pm_fpga_get_status(u32 *value);
483 int zynqmp_pm_write_ggs(u32 index, u32 value);
484 int zynqmp_pm_read_ggs(u32 index, u32 *value);
485 int zynqmp_pm_write_pggs(u32 index, u32 value);
486 int zynqmp_pm_read_pggs(u32 index, u32 *value);
487 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
488 int zynqmp_pm_set_boot_health_status(u32 value);
489 int zynqmp_pm_pinctrl_request(const u32 pin);
490 int zynqmp_pm_pinctrl_release(const u32 pin);
491 int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id);
492 int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id);
493 int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
494 u32 *value);
495 int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
496 u32 value);
497 int zynqmp_pm_load_pdi(const u32 src, const u64 address);
498 int zynqmp_pm_register_notifier(const u32 node, const u32 event,
499 const u32 wake, const u32 enable);
500 int zynqmp_pm_feature(const u32 api_id);
501 int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
502 int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value);
503 int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload);
504 int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
505 int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
506 int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
507 u32 value);
508 #else
zynqmp_pm_get_api_version(u32 * version)509 static inline int zynqmp_pm_get_api_version(u32 *version)
510 {
511 return -ENODEV;
512 }
513
zynqmp_pm_get_chipid(u32 * idcode,u32 * version)514 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
515 {
516 return -ENODEV;
517 }
518
zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,u32 * out)519 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
520 u32 *out)
521 {
522 return -ENODEV;
523 }
524
zynqmp_pm_clock_enable(u32 clock_id)525 static inline int zynqmp_pm_clock_enable(u32 clock_id)
526 {
527 return -ENODEV;
528 }
529
zynqmp_pm_clock_disable(u32 clock_id)530 static inline int zynqmp_pm_clock_disable(u32 clock_id)
531 {
532 return -ENODEV;
533 }
534
zynqmp_pm_clock_getstate(u32 clock_id,u32 * state)535 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
536 {
537 return -ENODEV;
538 }
539
zynqmp_pm_clock_setdivider(u32 clock_id,u32 divider)540 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
541 {
542 return -ENODEV;
543 }
544
zynqmp_pm_clock_getdivider(u32 clock_id,u32 * divider)545 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
546 {
547 return -ENODEV;
548 }
549
zynqmp_pm_clock_setrate(u32 clock_id,u64 rate)550 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
551 {
552 return -ENODEV;
553 }
554
zynqmp_pm_clock_getrate(u32 clock_id,u64 * rate)555 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
556 {
557 return -ENODEV;
558 }
559
zynqmp_pm_clock_setparent(u32 clock_id,u32 parent_id)560 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
561 {
562 return -ENODEV;
563 }
564
zynqmp_pm_clock_getparent(u32 clock_id,u32 * parent_id)565 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
566 {
567 return -ENODEV;
568 }
569
zynqmp_pm_set_pll_frac_mode(u32 clk_id,u32 mode)570 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
571 {
572 return -ENODEV;
573 }
574
zynqmp_pm_get_pll_frac_mode(u32 clk_id,u32 * mode)575 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
576 {
577 return -ENODEV;
578 }
579
zynqmp_pm_set_pll_frac_data(u32 clk_id,u32 data)580 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
581 {
582 return -ENODEV;
583 }
584
zynqmp_pm_get_pll_frac_data(u32 clk_id,u32 * data)585 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
586 {
587 return -ENODEV;
588 }
589
zynqmp_pm_set_sd_tapdelay(u32 node_id,u32 type,u32 value)590 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
591 {
592 return -ENODEV;
593 }
594
zynqmp_pm_sd_dll_reset(u32 node_id,u32 type)595 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
596 {
597 return -ENODEV;
598 }
599
zynqmp_pm_ospi_mux_select(u32 dev_id,u32 select)600 static inline int zynqmp_pm_ospi_mux_select(u32 dev_id, u32 select)
601 {
602 return -ENODEV;
603 }
604
zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,const enum zynqmp_pm_reset_action assert_flag)605 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
606 const enum zynqmp_pm_reset_action assert_flag)
607 {
608 return -ENODEV;
609 }
610
zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,u32 * status)611 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
612 u32 *status)
613 {
614 return -ENODEV;
615 }
616
zynqmp_pm_bootmode_read(u32 * ps_mode)617 static inline unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)
618 {
619 return -ENODEV;
620 }
621
zynqmp_pm_bootmode_write(u32 ps_mode)622 static inline int zynqmp_pm_bootmode_write(u32 ps_mode)
623 {
624 return -ENODEV;
625 }
626
zynqmp_pm_init_finalize(void)627 static inline int zynqmp_pm_init_finalize(void)
628 {
629 return -ENODEV;
630 }
631
zynqmp_pm_set_suspend_mode(u32 mode)632 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
633 {
634 return -ENODEV;
635 }
636
zynqmp_pm_request_node(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)637 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
638 const u32 qos,
639 const enum zynqmp_pm_request_ack ack)
640 {
641 return -ENODEV;
642 }
643
zynqmp_pm_release_node(const u32 node)644 static inline int zynqmp_pm_release_node(const u32 node)
645 {
646 return -ENODEV;
647 }
648
zynqmp_pm_set_requirement(const u32 node,const u32 capabilities,const u32 qos,const enum zynqmp_pm_request_ack ack)649 static inline int zynqmp_pm_set_requirement(const u32 node,
650 const u32 capabilities,
651 const u32 qos,
652 const enum zynqmp_pm_request_ack ack)
653 {
654 return -ENODEV;
655 }
656
zynqmp_pm_aes_engine(const u64 address,u32 * out)657 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
658 {
659 return -ENODEV;
660 }
661
zynqmp_pm_sha_hash(const u64 address,const u32 size,const u32 flags)662 static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
663 const u32 flags)
664 {
665 return -ENODEV;
666 }
667
zynqmp_pm_fpga_load(const u64 address,const u32 size,const u32 flags)668 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
669 const u32 flags)
670 {
671 return -ENODEV;
672 }
673
zynqmp_pm_fpga_get_status(u32 * value)674 static inline int zynqmp_pm_fpga_get_status(u32 *value)
675 {
676 return -ENODEV;
677 }
678
zynqmp_pm_write_ggs(u32 index,u32 value)679 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
680 {
681 return -ENODEV;
682 }
683
zynqmp_pm_read_ggs(u32 index,u32 * value)684 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
685 {
686 return -ENODEV;
687 }
688
zynqmp_pm_write_pggs(u32 index,u32 value)689 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
690 {
691 return -ENODEV;
692 }
693
zynqmp_pm_read_pggs(u32 index,u32 * value)694 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
695 {
696 return -ENODEV;
697 }
698
zynqmp_pm_system_shutdown(const u32 type,const u32 subtype)699 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
700 {
701 return -ENODEV;
702 }
703
zynqmp_pm_set_boot_health_status(u32 value)704 static inline int zynqmp_pm_set_boot_health_status(u32 value)
705 {
706 return -ENODEV;
707 }
708
zynqmp_pm_pinctrl_request(const u32 pin)709 static inline int zynqmp_pm_pinctrl_request(const u32 pin)
710 {
711 return -ENODEV;
712 }
713
zynqmp_pm_pinctrl_release(const u32 pin)714 static inline int zynqmp_pm_pinctrl_release(const u32 pin)
715 {
716 return -ENODEV;
717 }
718
zynqmp_pm_pinctrl_get_function(const u32 pin,u32 * id)719 static inline int zynqmp_pm_pinctrl_get_function(const u32 pin, u32 *id)
720 {
721 return -ENODEV;
722 }
723
zynqmp_pm_is_function_supported(const u32 api_id,const u32 id)724 static inline int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
725 {
726 return -ENODEV;
727 }
728
zynqmp_pm_pinctrl_set_function(const u32 pin,const u32 id)729 static inline int zynqmp_pm_pinctrl_set_function(const u32 pin, const u32 id)
730 {
731 return -ENODEV;
732 }
733
zynqmp_pm_pinctrl_get_config(const u32 pin,const u32 param,u32 * value)734 static inline int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param,
735 u32 *value)
736 {
737 return -ENODEV;
738 }
739
zynqmp_pm_pinctrl_set_config(const u32 pin,const u32 param,u32 value)740 static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param,
741 u32 value)
742 {
743 return -ENODEV;
744 }
745
zynqmp_pm_load_pdi(const u32 src,const u64 address)746 static inline int zynqmp_pm_load_pdi(const u32 src, const u64 address)
747 {
748 return -ENODEV;
749 }
750
zynqmp_pm_register_notifier(const u32 node,const u32 event,const u32 wake,const u32 enable)751 static inline int zynqmp_pm_register_notifier(const u32 node, const u32 event,
752 const u32 wake, const u32 enable)
753 {
754 return -ENODEV;
755 }
756
zynqmp_pm_feature(const u32 api_id)757 static inline int zynqmp_pm_feature(const u32 api_id)
758 {
759 return -ENODEV;
760 }
761
zynqmp_pm_set_feature_config(enum pm_feature_config_id id,u32 value)762 static inline int zynqmp_pm_set_feature_config(enum pm_feature_config_id id,
763 u32 value)
764 {
765 return -ENODEV;
766 }
767
zynqmp_pm_get_feature_config(enum pm_feature_config_id id,u32 * payload)768 static inline int zynqmp_pm_get_feature_config(enum pm_feature_config_id id,
769 u32 *payload)
770 {
771 return -ENODEV;
772 }
773
zynqmp_pm_register_sgi(u32 sgi_num,u32 reset)774 static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset)
775 {
776 return -ENODEV;
777 }
778
zynqmp_pm_set_sd_config(u32 node,enum pm_sd_config_type config,u32 value)779 static inline int zynqmp_pm_set_sd_config(u32 node,
780 enum pm_sd_config_type config,
781 u32 value)
782 {
783 return -ENODEV;
784 }
785
zynqmp_pm_set_gem_config(u32 node,enum pm_gem_config_type config,u32 value)786 static inline int zynqmp_pm_set_gem_config(u32 node,
787 enum pm_gem_config_type config,
788 u32 value)
789 {
790 return -ENODEV;
791 }
792
793 #endif
794
795 #endif /* __FIRMWARE_ZYNQMP_H__ */
796