Searched refs:X86_FEATURE_SME_COHERENT (Results 1 – 4 of 4) sorted by relevance
421 #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ macro
424 #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ macro
288 return !cpu_feature_enabled(X86_FEATURE_SME_COHERENT); in amd_enc_cache_flush_required()
463 if (this_cpu_has(X86_FEATURE_SME_COHERENT) || npages == 0 || in sev_clflush_pages()2303 if (boot_cpu_has(X86_FEATURE_SME_COHERENT)) { in sev_flush_encrypted_page()