Searched refs:X86_CONFIG (Results 1 – 4 of 4) sorted by relevance
| /linux-6.1.9/arch/x86/kernel/cpu/resctrl/ |
| D | pseudo_lock.c | 1073 perf_miss_attr.config = X86_CONFIG(.event = 0xd1, in measure_l2_residency()
1075 perf_hit_attr.config = X86_CONFIG(.event = 0xd1, in measure_l2_residency()
1112 perf_hit_attr.config = X86_CONFIG(.event = 0x2e, in measure_l3_residency()
1114 perf_miss_attr.config = X86_CONFIG(.event = 0x2e, in measure_l3_residency()
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| /linux-6.1.9/arch/x86/events/zhaoxin/ |
| D | core.c | 564 X86_CONFIG(.event = 0x01, .umask = 0x01, .inv = 0x01, .cmask = 0x01); in zhaoxin_pmu_init()
567 X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0); in zhaoxin_pmu_init()
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| /linux-6.1.9/arch/x86/events/intel/ |
| D | core.c | 3695 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
3723 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_snb()
3747 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_precdist()
3829 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01); in is_mem_loads_event()
3834 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82); in is_mem_loads_aux_event()
4361 X86_CONFIG(.event=0xc0, .umask=0x01)) { in bdw_limit_period()
5870 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
5873 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
6058 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
6061 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
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| /linux-6.1.9/arch/x86/events/ |
| D | perf_event.h | 640 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value macro
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