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Searched refs:WatermarkRow (Results 1 – 25 of 38) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
Ddcn316_clk_mgr.c366 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn316_build_watermark_ranges()
367 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn316_build_watermark_ranges()
369 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
370 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges()
372 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in dcn316_build_watermark_ranges()
374 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn316_build_watermark_ranges()
377 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn316_build_watermark_ranges()
380 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn316_build_watermark_ranges()
385 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn316_build_watermark_ranges()
386 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges()
[all …]
Ddcn316_smu.h98 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c399 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in vg_build_watermark_ranges()
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in vg_build_watermark_ranges()
402 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
403 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
405 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in vg_build_watermark_ranges()
407 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in vg_build_watermark_ranges()
410 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in vg_build_watermark_ranges()
413 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in vg_build_watermark_ranges()
418 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in vg_build_watermark_ranges()
419 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
[all …]
Ddcn301_smu.h77 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
131 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c430 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn31_build_watermark_ranges()
431 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn31_build_watermark_ranges()
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
434 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
436 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in dcn31_build_watermark_ranges()
438 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn31_build_watermark_ranges()
441 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn31_build_watermark_ranges()
444 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn31_build_watermark_ranges()
449 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn31_build_watermark_ranges()
450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
[all …]
Ddcn31_smu.h74 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
231 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
Ddcn315_clk_mgr.c374 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn315_build_watermark_ranges()
375 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn315_build_watermark_ranges()
377 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
378 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges()
380 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in dcn315_build_watermark_ranges()
382 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn315_build_watermark_ranges()
385 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn315_build_watermark_ranges()
388 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn315_build_watermark_ranges()
393 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn315_build_watermark_ranges()
394 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges()
[all …]
Ddcn315_smu.h90 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
Ddcn314_clk_mgr.c449 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn314_build_watermark_ranges()
450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn314_build_watermark_ranges()
452 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
453 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
455 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { in dcn314_build_watermark_ranges()
457 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; in dcn314_build_watermark_ranges()
460 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = in dcn314_build_watermark_ranges()
463 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = in dcn314_build_watermark_ranges()
468 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn314_build_watermark_ranges()
469 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
[all …]
Ddcn314_smu.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu_helper.c737 table->WatermarkRow[1][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
741 table->WatermarkRow[1][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
745 table->WatermarkRow[1][i].MinUclk = in smu_set_watermarks_for_clocks_ranges()
749 table->WatermarkRow[1][i].MaxUclk = in smu_set_watermarks_for_clocks_ranges()
753 table->WatermarkRow[1][i].WmSetting = (uint8_t) in smu_set_watermarks_for_clocks_ranges()
758 table->WatermarkRow[0][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
762 table->WatermarkRow[0][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
766 table->WatermarkRow[0][i].MinUclk = in smu_set_watermarks_for_clocks_ranges()
770 table->WatermarkRow[0][i].MaxUclk = in smu_set_watermarks_for_clocks_ranges()
774 table->WatermarkRow[0][i].WmSetting = (uint8_t) in smu_set_watermarks_for_clocks_ranges()
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dsmu_v13_0_4_ppt.c646 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
648 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table()
650 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v13_0_4_set_watermarks_table()
652 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v13_0_4_set_watermarks_table()
655 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v13_0_4_set_watermarks_table()
660 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
662 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table()
664 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v13_0_4_set_watermarks_table()
666 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in smu_v13_0_4_set_watermarks_table()
669 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in smu_v13_0_4_set_watermarks_table()
Dsmu_v13_0_5_ppt.c415 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
417 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table()
419 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in smu_v13_0_5_set_watermarks_table()
421 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in smu_v13_0_5_set_watermarks_table()
424 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in smu_v13_0_5_set_watermarks_table()
429 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
431 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table()
433 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in smu_v13_0_5_set_watermarks_table()
435 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in smu_v13_0_5_set_watermarks_table()
438 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in smu_v13_0_5_set_watermarks_table()
Dyellow_carp_ppt.c498 table->WatermarkRow[WM_DCFCLK][i].MinClock = in yellow_carp_set_watermarks_table()
500 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
502 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in yellow_carp_set_watermarks_table()
504 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in yellow_carp_set_watermarks_table()
507 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in yellow_carp_set_watermarks_table()
512 table->WatermarkRow[WM_SOCCLK][i].MinClock = in yellow_carp_set_watermarks_table()
514 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
516 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in yellow_carp_set_watermarks_table()
518 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in yellow_carp_set_watermarks_table()
521 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in yellow_carp_set_watermarks_table()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_clk_mgr.c343 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
344 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
345 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
346 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
347 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i; in dcn3_notify_wm_ranges()
348 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries… in dcn3_notify_wm_ranges()
Ddcn30_smu11_driver_if.h52 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c1056 table->WatermarkRow[WM_DCFCLK][i].MinClock = in renoir_set_watermarks_table()
1058 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in renoir_set_watermarks_table()
1060 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in renoir_set_watermarks_table()
1062 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in renoir_set_watermarks_table()
1065 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in renoir_set_watermarks_table()
1067 table->WatermarkRow[WM_DCFCLK][i].WmType = in renoir_set_watermarks_table()
1072 table->WatermarkRow[WM_SOCCLK][i].MinClock = in renoir_set_watermarks_table()
1074 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in renoir_set_watermarks_table()
1076 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in renoir_set_watermarks_table()
1078 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in renoir_set_watermarks_table()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
Ddcn32_smu13_driver_if.h41 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; member
Dsmu13_driver_if.h75 WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES]; member
/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/inc/
Dsmu10_driver_if.h70 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu13_driver_if_v13_0_5.h73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu12_driver_if.h73 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu13_driver_if_yellow_carp.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
Dsmu11_driver_if_vangogh.h72 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; member
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dvangogh_ppt.c1609 table->WatermarkRow[WM_DCFCLK][i].MinClock = in vangogh_set_watermarks_table()
1611 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in vangogh_set_watermarks_table()
1613 table->WatermarkRow[WM_DCFCLK][i].MinMclk = in vangogh_set_watermarks_table()
1615 table->WatermarkRow[WM_DCFCLK][i].MaxMclk = in vangogh_set_watermarks_table()
1618 table->WatermarkRow[WM_DCFCLK][i].WmSetting = in vangogh_set_watermarks_table()
1623 table->WatermarkRow[WM_SOCCLK][i].MinClock = in vangogh_set_watermarks_table()
1625 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in vangogh_set_watermarks_table()
1627 table->WatermarkRow[WM_SOCCLK][i].MinMclk = in vangogh_set_watermarks_table()
1629 table->WatermarkRow[WM_SOCCLK][i].MaxMclk = in vangogh_set_watermarks_table()
1632 table->WatermarkRow[WM_SOCCLK][i].WmSetting = in vangogh_set_watermarks_table()

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