Searched refs:WR_CONFIRM (Results 1 – 11 of 11) sorted by relevance
119 #define WR_CONFIRM (1 << 20) macro
98 #define WR_CONFIRM (1 << 20) macro
151 #define WR_CONFIRM (1 << 20) macro
269 #define WR_CONFIRM (1 << 20) macro
961 (wc ? WR_CONFIRM : 0)); in gfx_v9_0_write_data_to_reg()1043 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5310 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5319 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5344 WR_CONFIRM) | in gfx_v9_0_ring_emit_ce_meta()5366 WR_CONFIRM) | in gfx_v9_0_ring_emit_de_meta()5463 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()5469 cmd = WR_CONFIRM; in gfx_v9_0_ring_emit_wreg()
284 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()400 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()5472 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5481 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5620 WR_CONFIRM) | in gfx_v11_0_ring_emit_de_meta()5666 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()5672 cmd = WR_CONFIRM; in gfx_v11_0_ring_emit_wreg()
892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()6300 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6309 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6406 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()6412 cmd = WR_CONFIRM; in gfx_v8_0_ring_emit_wreg()7217 WR_CONFIRM) | in gfx_v8_0_ring_emit_ce_meta()7250 WR_CONFIRM) | in gfx_v8_0_ring_emit_de_meta()
3752 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()3860 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()8640 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8649 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8797 WR_CONFIRM) | in gfx_v10_0_ring_emit_ce_meta()8848 WR_CONFIRM) | in gfx_v10_0_ring_emit_de_meta()8894 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()8900 cmd = WR_CONFIRM; in gfx_v10_0_ring_emit_wreg()
1709 #define WR_CONFIRM (1 << 20) macro
1646 #define WR_CONFIRM (1 << 20) macro
1737 #define WR_CONFIRM (1 << 20) macro