Searched refs:WRITE_DATA_DST_SEL (Results 1 – 16 of 16) sorted by relevance
152 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
110 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
89 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
142 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
260 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()5189 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5197 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5205 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5213 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()6300 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6309 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()7216 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()7249 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
3250 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()4080 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4088 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4096 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4104 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
960 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()1043 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5310 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5319 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5343 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()5365 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
284 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()400 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()5472 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5481 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5619 WRITE_DATA_DST_SEL(8) | in gfx_v11_0_ring_emit_de_meta()
1700 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3752 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()3860 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()8640 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8649 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8796 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_ce_meta()8847 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_de_meta()
2341 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3742 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()5684 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5698 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5705 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5716 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5727 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5077 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5092 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5100 WRITE_DATA_DST_SEL(0))); in si_vm_flush()