1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* ********************************************************************* 3 * SB1250 Board Support Package 4 * 5 * Generic Bus Constants File: sb1250_genbus.h 6 * 7 * This module contains constants and macros useful for 8 * manipulating the SB1250's Generic Bus interface 9 * 10 * SB1250 specification level: User's manual 10/21/02 11 * BCM1280 specification level: User's Manual 11/14/03 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000, 2001, 2002, 2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 ********************************************************************* */ 19 20 21 #ifndef _SB1250_GENBUS_H 22 #define _SB1250_GENBUS_H 23 24 #include <asm/sibyte/sb1250_defs.h> 25 26 /* 27 * Generic Bus Region Configuration Registers (Table 11-4) 28 */ 29 30 #define S_IO_RDY_ACTIVE 0 31 #define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE) 32 33 #define S_IO_ENA_RDY 1 34 #define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY) 35 36 #define S_IO_WIDTH_SEL 2 37 #define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL) 38 #define K_IO_WIDTH_SEL_1 0 39 #define K_IO_WIDTH_SEL_2 1 40 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 41 || SIBYTE_HDR_FEATURE_CHIP(1480) 42 #define K_IO_WIDTH_SEL_1L 2 43 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 44 #define K_IO_WIDTH_SEL_4 3 45 #define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL) 46 #define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL) 47 48 #define S_IO_PARITY_ENA 4 49 #define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA) 50 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 51 || SIBYTE_HDR_FEATURE_CHIP(1480) 52 #define S_IO_BURST_EN 5 53 #define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN) 54 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 55 #define S_IO_PARITY_ODD 6 56 #define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD) 57 #define S_IO_NONMUX 7 58 #define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX) 59 60 #define S_IO_TIMEOUT 8 61 #define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT) 62 #define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT) 63 #define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT) 64 65 /* 66 * Generic Bus Region Size register (Table 11-5) 67 */ 68 69 #define S_IO_MULT_SIZE 0 70 #define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE) 71 #define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE) 72 #define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE) 73 74 #define S_IO_REGSIZE 16 /* # bits to shift size for this reg */ 75 76 /* 77 * Generic Bus Region Address (Table 11-6) 78 */ 79 80 #define S_IO_START_ADDR 0 81 #define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR) 82 #define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR) 83 #define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR) 84 85 #define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */ 86 87 #define M_IO_BLK_CACHE _SB_MAKEMASK1(15) 88 89 90 /* 91 * Generic Bus Timing 0 Registers (Table 11-7) 92 */ 93 94 #define S_IO_ALE_WIDTH 0 95 #define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH) 96 #define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH) 97 #define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH) 98 99 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 100 || SIBYTE_HDR_FEATURE_CHIP(1480) 101 #define M_IO_EARLY_CS _SB_MAKEMASK1(3) 102 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 103 104 #define S_IO_ALE_TO_CS 4 105 #define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS) 106 #define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS) 107 #define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS) 108 109 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 110 || SIBYTE_HDR_FEATURE_CHIP(1480) 111 #define S_IO_BURST_WIDTH _SB_MAKE64(6) 112 #define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH) 113 #define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH) 114 #define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH) 115 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 116 117 #define S_IO_CS_WIDTH 8 118 #define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH) 119 #define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH) 120 #define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH) 121 122 #define S_IO_RDY_SMPLE 13 123 #define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE) 124 #define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE) 125 #define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE) 126 127 128 /* 129 * Generic Bus Timing 1 Registers (Table 11-8) 130 */ 131 132 #define S_IO_ALE_TO_WRITE 0 133 #define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE) 134 #define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE) 135 #define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE) 136 137 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \ 138 || SIBYTE_HDR_FEATURE_CHIP(1480) 139 #define M_IO_RDY_SYNC _SB_MAKEMASK1(3) 140 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 141 142 #define S_IO_WRITE_WIDTH 4 143 #define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH) 144 #define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH) 145 #define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH) 146 147 #define S_IO_IDLE_CYCLE 8 148 #define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE) 149 #define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE) 150 #define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE) 151 152 #define S_IO_OE_TO_CS 12 153 #define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS) 154 #define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS) 155 #define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS) 156 157 #define S_IO_CS_TO_OE 14 158 #define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE) 159 #define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE) 160 #define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE) 161 162 /* 163 * Generic Bus Interrupt Status Register (Table 11-9) 164 */ 165 166 #define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8) 167 #define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0) 168 #define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1) 169 #define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2) 170 #define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3) 171 #define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4) 172 #define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5) 173 #define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6) 174 #define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7) 175 176 #define M_IO_RD_PAR_INT _SB_MAKEMASK1(9) 177 #define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10) 178 #define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11) 179 #define M_IO_MULT_CS_INT _SB_MAKEMASK1(12) 180 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 181 #define M_IO_COH_ERR _SB_MAKEMASK1(14) 182 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 183 184 185 /* 186 * Generic Bus Output Drive Control Register 0 (Table 14-18) 187 */ 188 189 #define S_IO_SLEW0 0 190 #define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0) 191 #define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0) 192 #define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0) 193 194 #define S_IO_DRV_A 2 195 #define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A) 196 #define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A) 197 #define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A) 198 199 #define S_IO_DRV_B 6 200 #define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B) 201 #define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B) 202 #define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B) 203 204 #define S_IO_DRV_C 10 205 #define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C) 206 #define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C) 207 #define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C) 208 209 #define S_IO_DRV_D 14 210 #define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D) 211 #define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D) 212 #define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D) 213 214 /* 215 * Generic Bus Output Drive Control Register 1 (Table 14-19) 216 */ 217 218 #define S_IO_DRV_E 2 219 #define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E) 220 #define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E) 221 #define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E) 222 223 #define S_IO_DRV_F 6 224 #define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F) 225 #define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F) 226 #define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F) 227 228 #define S_IO_SLEW1 8 229 #define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1) 230 #define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1) 231 #define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1) 232 233 #define S_IO_DRV_G 10 234 #define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G) 235 #define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G) 236 #define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G) 237 238 #define S_IO_SLEW2 12 239 #define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2) 240 #define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2) 241 #define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2) 242 243 #define S_IO_DRV_H 14 244 #define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H) 245 #define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H) 246 #define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H) 247 248 /* 249 * Generic Bus Output Drive Control Register 2 (Table 14-20) 250 */ 251 252 #define S_IO_DRV_J 2 253 #define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J) 254 #define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J) 255 #define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J) 256 257 #define S_IO_DRV_K 6 258 #define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K) 259 #define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K) 260 #define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K) 261 262 #define S_IO_DRV_L 10 263 #define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L) 264 #define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L) 265 #define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L) 266 267 #define S_IO_DRV_M 14 268 #define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M) 269 #define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M) 270 #define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M) 271 272 /* 273 * Generic Bus Output Drive Control Register 3 (Table 14-21) 274 */ 275 276 #define S_IO_SLEW3 0 277 #define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3) 278 #define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3) 279 #define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3) 280 281 #define S_IO_DRV_N 2 282 #define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N) 283 #define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N) 284 #define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N) 285 286 #define S_IO_DRV_P 6 287 #define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P) 288 #define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P) 289 #define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P) 290 291 #define S_IO_DRV_Q 10 292 #define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q) 293 #define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q) 294 #define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q) 295 296 #define S_IO_DRV_R 14 297 #define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R) 298 #define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R) 299 #define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R) 300 301 302 /* 303 * PCMCIA configuration register (Table 12-6) 304 */ 305 306 #define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0) 307 #define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1) 308 #define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2) 309 #define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3) 310 #define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4) 311 #define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5) 312 #define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6) 313 #define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7) 314 #define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8) 315 #define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9) 316 317 #if SIBYTE_HDR_FEATURE_CHIP(1480) 318 #define S_PCMCIA_MODE 16 319 #define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE) 320 #define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE) 321 #define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE) 322 323 #define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */ 324 #define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */ 325 #define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */ 326 #define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */ 327 #define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */ 328 #define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */ 329 #define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */ 330 #endif 331 332 333 /* 334 * PCMCIA status register (Table 12-7) 335 */ 336 337 #define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0) 338 #define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1) 339 #define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2) 340 #define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3) 341 #define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4) 342 #define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5) 343 #define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6) 344 #define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7) 345 #define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8) 346 #define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9) 347 #define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10) 348 349 /* 350 * GPIO Interrupt Type Register (table 13-3) 351 */ 352 353 #define K_GPIO_INTR_DISABLE 0 354 #define K_GPIO_INTR_EDGE 1 355 #define K_GPIO_INTR_LEVEL 2 356 #define K_GPIO_INTR_SPLIT 3 357 358 #define S_GPIO_INTR_TYPEX(n) (((n)/2)*2) 359 #define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n)) 360 #define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n)) 361 #define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n)) 362 363 #define S_GPIO_INTR_TYPE0 0 364 #define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0) 365 #define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0) 366 #define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0) 367 368 #define S_GPIO_INTR_TYPE2 2 369 #define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2) 370 #define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2) 371 #define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2) 372 373 #define S_GPIO_INTR_TYPE4 4 374 #define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4) 375 #define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4) 376 #define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4) 377 378 #define S_GPIO_INTR_TYPE6 6 379 #define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6) 380 #define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6) 381 #define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6) 382 383 #define S_GPIO_INTR_TYPE8 8 384 #define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8) 385 #define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8) 386 #define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8) 387 388 #define S_GPIO_INTR_TYPE10 10 389 #define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10) 390 #define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10) 391 #define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10) 392 393 #define S_GPIO_INTR_TYPE12 12 394 #define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12) 395 #define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12) 396 #define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12) 397 398 #define S_GPIO_INTR_TYPE14 14 399 #define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14) 400 #define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14) 401 #define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14) 402 403 #if SIBYTE_HDR_FEATURE_CHIP(1480) 404 405 /* 406 * GPIO Interrupt Additional Type Register 407 */ 408 409 #define K_GPIO_INTR_BOTHEDGE 0 410 #define K_GPIO_INTR_RISEEDGE 1 411 #define K_GPIO_INTR_UNPRED1 2 412 #define K_GPIO_INTR_UNPRED2 3 413 414 #define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2) 415 #define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n)) 416 #define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n)) 417 #define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n)) 418 419 #define S_GPIO_INTR_ATYPE0 0 420 #define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0) 421 #define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0) 422 #define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0) 423 424 #define S_GPIO_INTR_ATYPE2 2 425 #define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2) 426 #define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2) 427 #define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2) 428 429 #define S_GPIO_INTR_ATYPE4 4 430 #define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4) 431 #define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4) 432 #define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4) 433 434 #define S_GPIO_INTR_ATYPE6 6 435 #define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6) 436 #define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6) 437 #define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6) 438 439 #define S_GPIO_INTR_ATYPE8 8 440 #define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8) 441 #define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8) 442 #define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8) 443 444 #define S_GPIO_INTR_ATYPE10 10 445 #define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10) 446 #define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10) 447 #define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10) 448 449 #define S_GPIO_INTR_ATYPE12 12 450 #define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12) 451 #define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12) 452 #define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12) 453 454 #define S_GPIO_INTR_ATYPE14 14 455 #define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14) 456 #define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14) 457 #define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14) 458 #endif 459 460 461 #endif 462