| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 178 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
179 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gfxhub_v1_0_init_cache_regs()
181 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in gfxhub_v1_0_init_cache_regs()
183 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in gfxhub_v1_0_init_cache_regs()
184 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gfxhub_v1_0_init_cache_regs()
185 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in gfxhub_v1_0_init_cache_regs()
364 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_0_gart_disable()
|
| D | mmhub_v1_0.c | 164 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
165 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v1_0_init_cache_regs()
167 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in mmhub_v1_0_init_cache_regs()
169 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in mmhub_v1_0_init_cache_regs()
170 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in mmhub_v1_0_init_cache_regs()
171 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in mmhub_v1_0_init_cache_regs()
362 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v1_0_gart_disable()
|
| D | gmc_v7_0.c | 637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v7_0_gart_enable()
639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
641 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); in gmc_v7_0_gart_enable()
642 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gmc_v7_0_gart_enable()
643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); in gmc_v7_0_gart_enable()
755 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v7_0_gart_disable()
|
| D | gmc_v8_0.c | 860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in gmc_v8_0_gart_enable()
862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
864 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); in gmc_v8_0_gart_enable()
865 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in gmc_v8_0_gart_enable()
866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); in gmc_v8_0_gart_enable()
995 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v8_0_gart_disable()
|
| D | mmhub_v1_7.c | 184 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_7_init_cache_regs()
185 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); in mmhub_v1_7_init_cache_regs()
187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, in mmhub_v1_7_init_cache_regs()
189 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); in mmhub_v1_7_init_cache_regs()
190 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); in mmhub_v1_7_init_cache_regs()
191 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); in mmhub_v1_7_init_cache_regs()
372 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v1_7_gart_disable()
|
| D | amdgpu_gmc.h | 268 u64 VM_L2_CNTL; member
|
| D | gfxhub_v2_1.c | 582 adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL); in gfxhub_v2_1_save_regs()
616 WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, adev->gmc.VM_L2_CNTL); in gfxhub_v2_1_restore_regs()
|
| D | sid.h | 370 #define VM_L2_CNTL 0x500 macro
|
| /linux-6.1.9/drivers/gpu/drm/radeon/ |
| D | rv770.c | 918 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
965 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_disable()
995 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_agp_enable()
|
| D | rv770d.h | 642 #define VM_L2_CNTL 0x1400 macro
|
| D | nid.h | 104 #define VM_L2_CNTL 0x1400 macro
|
| D | ni.c | 1281 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cayman_pcie_gart_enable()
1362 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
|
| D | sid.h | 369 #define VM_L2_CNTL 0x1400 macro
|
| D | cikd.h | 487 #define VM_L2_CNTL 0x1400 macro
|
| D | r600.c | 1142 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1196 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_disable()
1234 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_agp_enable()
|
| D | evergreen.c | 2412 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2466 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_disable()
2495 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_agp_enable()
|
| D | evergreend.h | 1150 #define VM_L2_CNTL 0x1400 macro
|
| D | r600d.h | 587 #define VM_L2_CNTL 0x1400 macro
|
| D | si.c | 4300 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in si_pcie_gart_enable()
4388 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
|
| D | cik.c | 5439 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cik_pcie_gart_enable()
5556 WREG32(VM_L2_CNTL, in cik_pcie_gart_disable()
|