Searched refs:VIL (Results 1 – 3 of 3) sorted by relevance
21 - nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
32 - nvidia,rcv-sel: Integer. Select VIL/VIH receivers.
68 VIL = 23, /* 0x5C */ enumerator710 write_reg_le32(par->dc_regs, VIL, init->vil); in set_imstt_regvals()