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Searched refs:V3D_WRITE (Results 1 – 10 of 10) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/vc4/
Dvc4_irq.c108 V3D_WRITE(V3D_BPOA, bo->base.dma_addr + bin_bo_slot * vc4->bin_alloc_size); in vc4_overflow_mem_work()
109 V3D_WRITE(V3D_BPOS, bo->base.base.size); in vc4_overflow_mem_work()
110 V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM); in vc4_overflow_mem_work()
111 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM); in vc4_overflow_mem_work()
220 V3D_WRITE(V3D_INTCTL, intctl); in vc4_irq()
224 V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM); in vc4_irq()
260 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS); in vc4_irq_prepare()
277 V3D_WRITE(V3D_INTENA, V3D_INT_FLDONE | V3D_INT_FRDONE); in vc4_irq_enable()
292 V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS); in vc4_irq_disable()
295 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS); in vc4_irq_disable()
[all …]
Dvc4_perfmon.c59 V3D_WRITE(V3D_PCTRS(i), perfmon->events[i]); in vc4_perfmon_start()
62 V3D_WRITE(V3D_PCTRC, mask); in vc4_perfmon_start()
63 V3D_WRITE(V3D_PCTRE, V3D_PCTRE_EN | mask); in vc4_perfmon_start()
84 V3D_WRITE(V3D_PCTRE, 0); in vc4_perfmon_stop()
Dvc4_v3d.c170 V3D_WRITE(V3D_VPMBASE, 0); in vc4_v3d_init_hw()
303 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM); in bin_bo_alloc()
489 V3D_WRITE(V3D_BPOA, 0); in vc4_v3d_bind()
490 V3D_WRITE(V3D_BPOS, 0); in vc4_v3d_bind()
521 V3D_WRITE(V3D_BPOA, 0); in vc4_v3d_unbind()
522 V3D_WRITE(V3D_BPOS, 0); in vc4_v3d_unbind()
Dvc4_gem.c379 V3D_WRITE(V3D_CTNCA(thread), start); in submit_cl()
380 V3D_WRITE(V3D_CTNEA(thread), end); in submit_cl()
443 V3D_WRITE(V3D_L2CACTL, in vc4_flush_caches()
446 V3D_WRITE(V3D_SLCACTL, in vc4_flush_caches()
458 V3D_WRITE(V3D_L2CACTL, in vc4_flush_texture_caches()
461 V3D_WRITE(V3D_SLCACTL, in vc4_flush_texture_caches()
Dvc4_drv.h577 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) macro
/linux-6.1.9/drivers/gpu/drm/v3d/
Dv3d_mmu.c45 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL) | in v3d_mmu_flush_all()
48 V3D_WRITE(V3D_MMUC_CONTROL, in v3d_mmu_flush_all()
69 V3D_WRITE(V3D_MMU_PT_PA_BASE, v3d->pt_paddr >> V3D_MMU_PAGE_SHIFT); in v3d_mmu_set_page_table()
70 V3D_WRITE(V3D_MMU_CTL, in v3d_mmu_set_page_table()
79 V3D_WRITE(V3D_MMU_ILLEGAL_ADDR, in v3d_mmu_set_page_table()
82 V3D_WRITE(V3D_MMUC_CONTROL, V3D_MMUC_CONTROL_ENABLE); in v3d_mmu_set_page_table()
Dv3d_irq.c152 V3D_WRITE(V3D_HUB_INT_CLR, intsts); in v3d_hub_irq()
181 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL)); in v3d_hub_irq()
215 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); in v3d_irq_init()
263 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS); in v3d_irq_enable()
264 V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS); in v3d_irq_enable()
275 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0); in v3d_irq_disable()
280 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); in v3d_irq_disable()
Dv3d_sched.c193 V3D_WRITE(V3D_TFU_IIA, job->args.iia); in v3d_tfu_job_run()
194 V3D_WRITE(V3D_TFU_IIS, job->args.iis); in v3d_tfu_job_run()
195 V3D_WRITE(V3D_TFU_ICA, job->args.ica); in v3d_tfu_job_run()
196 V3D_WRITE(V3D_TFU_IUA, job->args.iua); in v3d_tfu_job_run()
197 V3D_WRITE(V3D_TFU_IOA, job->args.ioa); in v3d_tfu_job_run()
198 V3D_WRITE(V3D_TFU_IOS, job->args.ios); in v3d_tfu_job_run()
199 V3D_WRITE(V3D_TFU_COEF0, job->args.coef[0]); in v3d_tfu_job_run()
201 V3D_WRITE(V3D_TFU_COEF1, job->args.coef[1]); in v3d_tfu_job_run()
202 V3D_WRITE(V3D_TFU_COEF2, job->args.coef[2]); in v3d_tfu_job_run()
203 V3D_WRITE(V3D_TFU_COEF3, job->args.coef[3]); in v3d_tfu_job_run()
[all …]
Dv3d_drv.h204 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) macro
Dv3d_gem.c87 V3D_WRITE(V3D_HUB_AXICFG, V3D_HUB_AXICFG_MAX_LEN_MASK); in v3d_reset_by_bridge()