Searched refs:TSC1 (Results 1 – 9 of 9) sorted by relevance
48 u8 TSC1; member54 u8 TSC1; member181 txpn._byte_.TSC1 = iv[0];\
42 pattrib_iv[1] = txpn._byte_.TSC1;\53 pattrib_iv[0] = txpn._byte_.TSC1;\54 pattrib_iv[1] = (txpn._byte_.TSC1 | 0x20) & 0x7f;\68 pattrib_iv[1] = txpn._byte_.TSC1;\
45 u8 TSC1; member63 u8 TSC1; member201 dot11txpn._byte_.TSC1 = iv[0]; \
43 pattrib_iv[1] = dot11txpn._byte_.TSC1;\51 pattrib_iv[0] = dot11txpn._byte_.TSC1;\52 pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\65 pattrib_iv[1] = dot11txpn._byte_.TSC1; \
59 u8 TSC1; member75 u8 TSC1; member229 dot11txpn._byte_.TSC1 = iv[0];\
45 pattrib_iv[1] = dot11txpn._byte_.TSC1;\54 pattrib_iv[0] = dot11txpn._byte_.TSC1;\55 pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\68 pattrib_iv[1] = dot11txpn._byte_.TSC1;\
71 - description: TSC1 registers80 - description: TSC1 registers
71 #define TSC1 _MMIO(MCHBAR_MIRROR_BASE + 0x1001) macro
556 intel_uncore_write16(uncore, TSC1, in gen5_rps_enable()557 intel_uncore_read16(uncore, TSC1) | TSE); in gen5_rps_enable()