1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 /*
24  * link_encoder.h
25  *
26  *  Created on: Oct 6, 2015
27  *      Author: yonsun
28  */
29 
30 #ifndef LINK_ENCODER_H_
31 #define LINK_ENCODER_H_
32 
33 #include "grph_object_defs.h"
34 #include "signal_types.h"
35 #include "dc_types.h"
36 
37 struct dc_context;
38 struct encoder_set_dp_phy_pattern_param;
39 struct link_mst_stream_allocation_table;
40 struct dc_link_settings;
41 struct link_training_settings;
42 struct pipe_ctx;
43 
44 struct encoder_init_data {
45 	enum channel_id channel;
46 	struct graphics_object_id connector;
47 	enum hpd_source_id hpd_source;
48 	/* TODO: in DAL2, here was pointer to EventManagerInterface */
49 	struct graphics_object_id encoder;
50 	struct dc_context *ctx;
51 	enum transmitter transmitter;
52 };
53 
54 struct encoder_feature_support {
55 	union {
56 		struct {
57 			uint32_t IS_HBR2_CAPABLE:1;
58 			uint32_t IS_HBR3_CAPABLE:1;
59 			uint32_t IS_TPS3_CAPABLE:1;
60 			uint32_t IS_TPS4_CAPABLE:1;
61 			uint32_t HDMI_6GB_EN:1;
62 			uint32_t IS_DP2_CAPABLE:1;
63 			uint32_t IS_UHBR10_CAPABLE:1;
64 			uint32_t IS_UHBR13_5_CAPABLE:1;
65 			uint32_t IS_UHBR20_CAPABLE:1;
66 			uint32_t DP_IS_USB_C:1;
67 		} bits;
68 		uint32_t raw;
69 	} flags;
70 
71 	enum dc_color_depth max_hdmi_deep_color;
72 	unsigned int max_hdmi_pixel_clock;
73 	bool hdmi_ycbcr420_supported;
74 	bool dp_ycbcr420_supported;
75 	bool fec_supported;
76 };
77 
78 union dpcd_psr_configuration {
79 	struct {
80 		unsigned char ENABLE                    : 1;
81 		unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1;
82 		unsigned char CRC_VERIFICATION          : 1;
83 		unsigned char FRAME_CAPTURE_INDICATION  : 1;
84 		/* For eDP 1.4, PSR v2*/
85 		unsigned char LINE_CAPTURE_INDICATION   : 1;
86 		/* For eDP 1.4, PSR v2*/
87 		unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
88 		unsigned char ENABLE_PSR2               : 1;
89 		/* For eDP 1.5, PSR v2 w/ early transport */
90 		unsigned char EARLY_TRANSPORT_ENABLE    : 1;
91 	} bits;
92 	unsigned char raw;
93 };
94 
95 union dpcd_alpm_configuration {
96 	struct {
97 		unsigned char ENABLE                    : 1;
98 		unsigned char IRQ_HPD_ENABLE            : 1;
99 		unsigned char RESERVED                  : 6;
100 	} bits;
101 	unsigned char raw;
102 };
103 
104 union dpcd_sink_active_vtotal_control_mode {
105 	struct {
106 		unsigned char ENABLE                    : 1;
107 		unsigned char RESERVED                  : 7;
108 	} bits;
109 	unsigned char raw;
110 };
111 
112 union psr_error_status {
113 	struct {
114 		unsigned char LINK_CRC_ERROR        :1;
115 		unsigned char RFB_STORAGE_ERROR     :1;
116 		unsigned char VSC_SDP_ERROR         :1;
117 		unsigned char RESERVED              :5;
118 	} bits;
119 	unsigned char raw;
120 };
121 
122 union psr_sink_psr_status {
123 	struct {
124 	unsigned char SINK_SELF_REFRESH_STATUS  :3;
125 	unsigned char RESERVED                  :5;
126 	} bits;
127 	unsigned char raw;
128 };
129 
130 struct link_encoder {
131 	const struct link_encoder_funcs *funcs;
132 	int32_t aux_channel_offset;
133 	struct dc_context *ctx;
134 	struct graphics_object_id id;
135 	struct graphics_object_id connector;
136 	uint32_t output_signals;
137 	enum engine_id preferred_engine;
138 	struct encoder_feature_support features;
139 	enum transmitter transmitter;
140 	enum hpd_source_id hpd_source;
141 	bool usbc_combo_phy;
142 };
143 
144 struct link_enc_state {
145 
146 		uint32_t dphy_fec_en;
147 		uint32_t dphy_fec_ready_shadow;
148 		uint32_t dphy_fec_active_status;
149 		uint32_t dp_link_training_complete;
150 
151 };
152 
153 enum encoder_type_select {
154 	ENCODER_TYPE_DIG = 0,
155 	ENCODER_TYPE_HDMI_FRL = 1,
156 	ENCODER_TYPE_DP_128B132B = 2
157 };
158 
159 struct link_encoder_funcs {
160 	void (*read_state)(
161 			struct link_encoder *enc, struct link_enc_state *s);
162 	bool (*validate_output_with_stream)(
163 		struct link_encoder *enc, const struct dc_stream_state *stream);
164 	void (*hw_init)(struct link_encoder *enc);
165 	void (*setup)(struct link_encoder *enc,
166 		enum signal_type signal);
167 	void (*enable_tmds_output)(struct link_encoder *enc,
168 		enum clock_source_id clock_source,
169 		enum dc_color_depth color_depth,
170 		enum signal_type signal,
171 		uint32_t pixel_clock);
172 	void (*enable_dp_output)(struct link_encoder *enc,
173 		const struct dc_link_settings *link_settings,
174 		enum clock_source_id clock_source);
175 	void (*enable_dp_mst_output)(struct link_encoder *enc,
176 		const struct dc_link_settings *link_settings,
177 		enum clock_source_id clock_source);
178 	void (*enable_lvds_output)(struct link_encoder *enc,
179 		enum clock_source_id clock_source,
180 		uint32_t pixel_clock);
181 	void (*disable_output)(struct link_encoder *link_enc,
182 		enum signal_type signal);
183 	void (*dp_set_lane_settings)(struct link_encoder *enc,
184 		const struct dc_link_settings *link_settings,
185 		const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
186 	void (*dp_set_phy_pattern)(struct link_encoder *enc,
187 		const struct encoder_set_dp_phy_pattern_param *para);
188 	void (*update_mst_stream_allocation_table)(
189 		struct link_encoder *enc,
190 		const struct link_mst_stream_allocation_table *table);
191 	void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc,
192 			bool exit_link_training_required);
193 	void (*psr_program_secondary_packet)(struct link_encoder *enc,
194 				unsigned int sdp_transmit_line_num_deadline);
195 	void (*connect_dig_be_to_fe)(struct link_encoder *enc,
196 		enum engine_id engine,
197 		bool connect);
198 	void (*enable_hpd)(struct link_encoder *enc);
199 	void (*disable_hpd)(struct link_encoder *enc);
200 	bool (*is_dig_enabled)(struct link_encoder *enc);
201 	unsigned int (*get_dig_frontend)(struct link_encoder *enc);
202 	void (*destroy)(struct link_encoder **enc);
203 
204 	void (*fec_set_enable)(struct link_encoder *enc,
205 		bool enable);
206 
207 	void (*fec_set_ready)(struct link_encoder *enc,
208 		bool ready);
209 
210 	bool (*fec_is_active)(struct link_encoder *enc);
211 	bool (*is_in_alt_mode) (struct link_encoder *enc);
212 
213 	void (*get_max_link_cap)(struct link_encoder *enc,
214 		struct dc_link_settings *link_settings);
215 
216 	enum signal_type (*get_dig_mode)(
217 		struct link_encoder *enc);
218 	void (*set_dio_phy_mux)(
219 		struct link_encoder *enc,
220 		enum encoder_type_select sel,
221 		uint32_t hpo_inst);
222 	void (*set_dig_output_mode)(
223 			struct link_encoder *enc, uint8_t pix_per_container);
224 };
225 
226 /*
227  * Used to track assignments of links (display endpoints) to link encoders.
228  *
229  * Entry in link_enc_assignments table in struct resource_context.
230  * Entries only marked valid once encoder assigned to a link and invalidated once unassigned.
231  * Uses engine ID as identifier since PHY ID not relevant for USB4 DPIA endpoint.
232  */
233 struct link_enc_assignment {
234 	bool valid;
235 	struct display_endpoint_id ep_id;
236 	enum engine_id eng_id;
237 	struct dc_stream_state *stream;
238 };
239 
240 enum link_enc_cfg_mode {
241 	LINK_ENC_CFG_STEADY, /* Normal operation - use current_state. */
242 	LINK_ENC_CFG_TRANSIENT /* During commit state - use state to be committed. */
243 };
244 
245 enum dp2_link_mode {
246 	DP2_LINK_TRAINING_TPS1,
247 	DP2_LINK_TRAINING_TPS2,
248 	DP2_LINK_ACTIVE,
249 	DP2_TEST_PATTERN
250 };
251 
252 enum dp2_phy_tp_select {
253 	DP_DPHY_TP_SELECT_TPS1,
254 	DP_DPHY_TP_SELECT_TPS2,
255 	DP_DPHY_TP_SELECT_PRBS,
256 	DP_DPHY_TP_SELECT_CUSTOM,
257 	DP_DPHY_TP_SELECT_SQUARE
258 };
259 
260 enum dp2_phy_tp_prbs {
261 	DP_DPHY_TP_PRBS7,
262 	DP_DPHY_TP_PRBS9,
263 	DP_DPHY_TP_PRBS11,
264 	DP_DPHY_TP_PRBS15,
265 	DP_DPHY_TP_PRBS23,
266 	DP_DPHY_TP_PRBS31
267 };
268 
269 struct hpo_dp_link_enc_state {
270 	uint32_t   link_enc_enabled;
271 	uint32_t   link_mode;
272 	uint32_t   lane_count;
273 	uint32_t   slot_count[4];
274 	uint32_t   stream_src[4];
275 	uint32_t   vc_rate_x[4];
276 	uint32_t   vc_rate_y[4];
277 };
278 
279 struct hpo_dp_link_encoder {
280 	const struct hpo_dp_link_encoder_funcs *funcs;
281 	struct dc_context *ctx;
282 	int inst;
283 	enum engine_id preferred_engine;
284 	enum transmitter transmitter;
285 	enum hpd_source_id hpd_source;
286 };
287 
288 struct hpo_dp_link_encoder_funcs {
289 
290 	void (*enable_link_phy)(struct hpo_dp_link_encoder *enc,
291 		const struct dc_link_settings *link_settings,
292 		enum transmitter transmitter,
293 		enum hpd_source_id hpd_source);
294 
295 	void (*disable_link_phy)(struct hpo_dp_link_encoder *link_enc,
296 		enum signal_type signal);
297 
298 	void (*link_enable)(
299 			struct hpo_dp_link_encoder *enc,
300 			enum dc_lane_count num_lanes);
301 
302 	void (*link_disable)(
303 			struct hpo_dp_link_encoder *enc);
304 
305 	void (*set_link_test_pattern)(
306 			struct hpo_dp_link_encoder *enc,
307 			struct encoder_set_dp_phy_pattern_param *tp_params);
308 
309 	void (*update_stream_allocation_table)(
310 			struct hpo_dp_link_encoder *enc,
311 			const struct link_mst_stream_allocation_table *table);
312 
313 	void (*set_throttled_vcp_size)(
314 			struct hpo_dp_link_encoder *enc,
315 			uint32_t stream_encoder_inst,
316 			struct fixed31_32 avg_time_slots_per_mtp);
317 
318 	bool (*is_in_alt_mode) (
319 			struct hpo_dp_link_encoder *enc);
320 
321 	void (*read_state)(
322 			struct hpo_dp_link_encoder *enc,
323 			struct hpo_dp_link_enc_state *state);
324 
325 	void (*set_ffe)(
326 		struct hpo_dp_link_encoder *enc,
327 		const struct dc_link_settings *link_settings,
328 		uint8_t ffe_preset);
329 };
330 
331 #endif /* LINK_ENCODER_H_ */
332