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Searched refs:THM_CLK_CNTL__TMON_CLK_SEL__SHIFT (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dfiji_baco.c104 …WRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, …
Dci_baco.c120 …WRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, …
Dpolaris_baco.c99 …WRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, …
Dtonga_baco.c112 …RITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__TMON_CLK_SEL_MASK, THM_CLK_CNTL__TMON_CLK_SEL__SHIFT, 0, …
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dcik.c1826 (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT); in cik_program_aspm()
Dvi.c1222 (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT); in vi_program_aspm()
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_0_0_sh_mask.h266 #define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 macro
Dsmu_7_1_1_sh_mask.h264 #define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 macro
Dsmu_7_0_1_sh_mask.h264 #define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 macro
Dsmu_7_1_0_sh_mask.h262 #define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 macro
Dsmu_7_1_2_sh_mask.h264 #define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 macro
Dsmu_7_1_3_sh_mask.h292 #define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 macro