Searched refs:TEGRA234_CLK_PLLA_OUT0 (Results 1 – 2 of 2) sorted by relevance
90 #define TEGRA234_CLK_PLLA_OUT0 104U macro
84 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;98 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;112 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;126 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;140 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;154 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;168 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;278 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;291 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;304 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;[all …]