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Searched refs:SYS_CLK_UART0 (Results 1 – 3 of 3) sorted by relevance

/linux-6.1.9/include/dt-bindings/clock/
Dpistachio-clk.h158 #define SYS_CLK_UART0 10 macro
/linux-6.1.9/drivers/clk/pistachio/
Dclk-pistachio.c285 GATE(SYS_CLK_UART0, "uart0_sys", "sys", 0x8, 10),
/linux-6.1.9/arch/mips/boot/dts/img/
Dpistachio.dtsi257 clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;