1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *  linux/drivers/acorn/scsi/acornscsi.h
4  *
5  *  Copyright (C) 1997 Russell King
6  *
7  *  Acorn SCSI driver
8  */
9 #ifndef ACORNSCSI_H
10 #define ACORNSCSI_H
11 
12 /* SBIC registers */
13 #define SBIC_OWNID		0
14 #define OWNID_FS1		(1<<7)
15 #define OWNID_FS2		(1<<6)
16 #define OWNID_EHP		(1<<4)
17 #define OWNID_EAF		(1<<3)
18 
19 #define SBIC_CTRL		1
20 #define CTRL_DMAMODE		(1<<7)
21 #define CTRL_DMADBAMODE		(1<<6)
22 #define CTRL_DMABURST		(1<<5)
23 #define CTRL_DMAPOLLED		0
24 #define CTRL_HHP		(1<<4)
25 #define CTRL_EDI		(1<<3)
26 #define CTRL_IDI		(1<<2)
27 #define CTRL_HA			(1<<1)
28 #define CTRL_HSP		(1<<0)
29 
30 #define SBIC_TIMEOUT		2
31 #define SBIC_TOTSECTS		3
32 #define SBIC_TOTHEADS		4
33 #define SBIC_TOTCYLH		5
34 #define SBIC_TOTCYLL		6
35 #define SBIC_LOGADDRH		7
36 #define SBIC_LOGADDRM2		8
37 #define SBIC_LOGADDRM1		9
38 #define SBIC_LOGADDRL		10
39 #define SBIC_SECTORNUM		11
40 #define SBIC_HEADNUM		12
41 #define SBIC_CYLH		13
42 #define SBIC_CYLL		14
43 #define SBIC_TARGETLUN		15
44 #define TARGETLUN_TLV		(1<<7)
45 #define TARGETLUN_DOK		(1<<6)
46 
47 #define SBIC_CMNDPHASE		16
48 #define SBIC_SYNCHTRANSFER	17
49 #define SYNCHTRANSFER_OF0	0x00
50 #define SYNCHTRANSFER_OF1	0x01
51 #define SYNCHTRANSFER_OF2	0x02
52 #define SYNCHTRANSFER_OF3	0x03
53 #define SYNCHTRANSFER_OF4	0x04
54 #define SYNCHTRANSFER_OF5	0x05
55 #define SYNCHTRANSFER_OF6	0x06
56 #define SYNCHTRANSFER_OF7	0x07
57 #define SYNCHTRANSFER_OF8	0x08
58 #define SYNCHTRANSFER_OF9	0x09
59 #define SYNCHTRANSFER_OF10	0x0A
60 #define SYNCHTRANSFER_OF11	0x0B
61 #define SYNCHTRANSFER_OF12	0x0C
62 #define SYNCHTRANSFER_8DBA	0x00
63 #define SYNCHTRANSFER_2DBA	0x20
64 #define SYNCHTRANSFER_3DBA	0x30
65 #define SYNCHTRANSFER_4DBA	0x40
66 #define SYNCHTRANSFER_5DBA	0x50
67 #define SYNCHTRANSFER_6DBA	0x60
68 #define SYNCHTRANSFER_7DBA	0x70
69 
70 #define SBIC_TRANSCNTH		18
71 #define SBIC_TRANSCNTM		19
72 #define SBIC_TRANSCNTL		20
73 #define SBIC_DESTID		21
74 #define DESTID_SCC		(1<<7)
75 #define DESTID_DPD		(1<<6)
76 
77 #define SBIC_SOURCEID		22
78 #define SOURCEID_ER		(1<<7)
79 #define SOURCEID_ES		(1<<6)
80 #define SOURCEID_DSP		(1<<5)
81 #define SOURCEID_SIV		(1<<4)
82 
83 #define SBIC_SSR		23
84 #define SBIC_CMND		24
85 #define CMND_RESET		0x00
86 #define CMND_ABORT		0x01
87 #define CMND_ASSERTATN		0x02
88 #define CMND_NEGATEACK		0x03
89 #define CMND_DISCONNECT		0x04
90 #define CMND_RESELECT		0x05
91 #define CMND_SELWITHATN		0x06
92 #define CMND_SELECT		0x07
93 #define CMND_SELECTATNTRANSFER	0x08
94 #define CMND_SELECTTRANSFER	0x09
95 #define CMND_RESELECTRXDATA	0x0A
96 #define CMND_RESELECTTXDATA	0x0B
97 #define CMND_WAITFORSELRECV	0x0C
98 #define CMND_SENDSTATCMD	0x0D
99 #define CMND_SENDDISCONNECT	0x0E
100 #define CMND_SETIDI		0x0F
101 #define CMND_RECEIVECMD		0x10
102 #define CMND_RECEIVEDTA		0x11
103 #define CMND_RECEIVEMSG		0x12
104 #define CMND_RECEIVEUSP		0x13
105 #define CMND_SENDCMD		0x14
106 #define CMND_SENDDATA		0x15
107 #define CMND_SENDMSG		0x16
108 #define CMND_SENDUSP		0x17
109 #define CMND_TRANSLATEADDR	0x18
110 #define CMND_XFERINFO		0x20
111 #define CMND_SBT		(1<<7)
112 
113 #define SBIC_DATA		25
114 #define SBIC_ASR		26
115 #define ASR_INT			(1<<7)
116 #define ASR_LCI			(1<<6)
117 #define ASR_BSY			(1<<5)
118 #define ASR_CIP			(1<<4)
119 #define ASR_PE			(1<<1)
120 #define ASR_DBR			(1<<0)
121 
122 /* DMAC registers */
123 #define DMAC_INIT		0x00
124 #define INIT_8BIT		(1)
125 
126 #define DMAC_CHANNEL		0x80
127 #define CHANNEL_0		0x00
128 #define CHANNEL_1		0x01
129 #define CHANNEL_2		0x02
130 #define CHANNEL_3		0x03
131 
132 #define DMAC_TXCNTLO		0x01
133 #define DMAC_TXCNTHI		0x81
134 #define DMAC_TXADRLO		0x02
135 #define DMAC_TXADRMD		0x82
136 #define DMAC_TXADRHI		0x03
137 
138 #define DMAC_DEVCON0		0x04
139 #define DEVCON0_AKL		(1<<7)
140 #define DEVCON0_RQL		(1<<6)
141 #define DEVCON0_EXW		(1<<5)
142 #define DEVCON0_ROT		(1<<4)
143 #define DEVCON0_CMP		(1<<3)
144 #define DEVCON0_DDMA		(1<<2)
145 #define DEVCON0_AHLD		(1<<1)
146 #define DEVCON0_MTM		(1<<0)
147 
148 #define DMAC_DEVCON1		0x84
149 #define DEVCON1_WEV		(1<<1)
150 #define DEVCON1_BHLD		(1<<0)
151 
152 #define DMAC_MODECON		0x05
153 #define MODECON_WOED		0x01
154 #define MODECON_VERIFY		0x00
155 #define MODECON_READ		0x04
156 #define MODECON_WRITE		0x08
157 #define MODECON_AUTOINIT	0x10
158 #define MODECON_ADDRDIR		0x20
159 #define MODECON_DEMAND		0x00
160 #define MODECON_SINGLE		0x40
161 #define MODECON_BLOCK		0x80
162 #define MODECON_CASCADE		0xC0
163 
164 #define DMAC_STATUS		0x85
165 #define STATUS_TC0		(1<<0)
166 #define STATUS_RQ0		(1<<4)
167 
168 #define DMAC_TEMPLO		0x06
169 #define DMAC_TEMPHI		0x86
170 #define DMAC_REQREG		0x07
171 #define DMAC_MASKREG		0x87
172 #define MASKREG_M0		0x01
173 #define MASKREG_M1		0x02
174 #define MASKREG_M2		0x04
175 #define MASKREG_M3		0x08
176 
177 /* miscellaneous internal variables */
178 
179 #define MASK_ON		(MASKREG_M3|MASKREG_M2|MASKREG_M1|MASKREG_M0)
180 #define MASK_OFF	(MASKREG_M3|MASKREG_M2|MASKREG_M1)
181 
182 /*
183  * SCSI driver phases
184  */
185 typedef enum {
186     PHASE_IDLE,					/* we're not planning on doing anything	 */
187     PHASE_CONNECTING,				/* connecting to a target		 */
188     PHASE_CONNECTED,				/* connected to a target		 */
189     PHASE_MSGOUT,				/* message out to device		 */
190     PHASE_RECONNECTED,				/* reconnected				 */
191     PHASE_COMMANDPAUSED,			/* command partly sent			 */
192     PHASE_COMMAND,				/* command all sent			 */
193     PHASE_DATAOUT,				/* data out to device			 */
194     PHASE_DATAIN,				/* data in from device			 */
195     PHASE_STATUSIN,				/* status in from device		 */
196     PHASE_MSGIN,				/* message in from device		 */
197     PHASE_DONE,					/* finished				 */
198     PHASE_ABORTED,				/* aborted				 */
199     PHASE_DISCONNECT,				/* disconnecting			 */
200 } phase_t;
201 
202 /*
203  * After interrupt, what to do now
204  */
205 typedef enum {
206     INTR_IDLE,					/* not expecting another IRQ		 */
207     INTR_NEXT_COMMAND,				/* start next command			 */
208     INTR_PROCESSING,				/* interrupt routine still processing	 */
209 } intr_ret_t;
210 
211 /*
212  * DMA direction
213  */
214 typedef enum {
215     DMA_OUT,					/* DMA from memory to chip		*/
216     DMA_IN					/* DMA from chip to memory		*/
217 } dmadir_t;
218 
219 /*
220  * Synchronous transfer state
221  */
222 typedef enum {					/* Synchronous transfer state		*/
223     SYNC_ASYNCHRONOUS,				/* don't negotiate synchronous transfers*/
224     SYNC_NEGOCIATE,				/* start negotiation			*/
225     SYNC_SENT_REQUEST,				/* sent SDTR message			*/
226     SYNC_COMPLETED,				/* received SDTR reply			*/
227 } syncxfer_t;
228 
229 /*
230  * Command type
231  */
232 typedef enum {					/* command type				*/
233     CMD_READ,					/* READ_6, READ_10, READ_12		*/
234     CMD_WRITE,					/* WRITE_6, WRITE_10, WRITE_12		*/
235     CMD_MISC,					/* Others				*/
236 } cmdtype_t;
237 
238 /*
239  * Data phase direction
240  */
241 typedef enum {					/* Data direction			*/
242     DATADIR_IN,					/* Data in phase expected		*/
243     DATADIR_OUT					/* Data out phase expected		*/
244 } datadir_t;
245 
246 #include "queue.h"
247 #include "msgqueue.h"
248 
249 #define STATUS_BUFFER_SIZE	32
250 /*
251  * This is used to dump the previous states of the SBIC
252  */
253 struct status_entry {
254 	unsigned long	when;
255 	unsigned char	ssr;
256 	unsigned char	ph;
257 	unsigned char	irq;
258 	unsigned char	unused;
259 };
260 
261 #define ADD_STATUS(_q,_ssr,_ph,_irq) \
262 ({									\
263 	host->status[(_q)][host->status_ptr[(_q)]].when = jiffies;	\
264 	host->status[(_q)][host->status_ptr[(_q)]].ssr  = (_ssr);	\
265 	host->status[(_q)][host->status_ptr[(_q)]].ph   = (_ph);	\
266 	host->status[(_q)][host->status_ptr[(_q)]].irq  = (_irq);	\
267 	host->status_ptr[(_q)] = (host->status_ptr[(_q)] + 1) & (STATUS_BUFFER_SIZE - 1); \
268 })
269 
270 /*
271  * AcornSCSI host specific data
272  */
273 typedef struct acornscsi_hostdata {
274     /* miscellaneous */
275     struct Scsi_Host	*host;			/* host					*/
276     struct scsi_cmnd	*SCpnt;			/* currently processing command		*/
277     struct scsi_cmnd	*origSCpnt;		/* original connecting command		*/
278     void __iomem	*base;			/* memc base address 			*/
279     void __iomem	*fast;			/* fast ioc base address		*/
280 
281     /* driver information */
282     struct {
283 	unsigned int	irq;			/* interrupt				*/
284 	phase_t		phase;			/* current phase			*/
285 
286 	struct {
287 	    unsigned char	target;		/* reconnected target			*/
288 	    unsigned char	lun;		/* reconnected lun			*/
289 	    unsigned char	tag;		/* reconnected tag			*/
290 	} reconnected;
291 
292 	struct scsi_pointer	SCp;			/* current commands data pointer	*/
293 
294 	MsgQueue_t	msgs;
295 
296 	unsigned short	last_message;		/* last message to be sent		*/
297 	unsigned char	disconnectable:1;	/* this command can be disconnected	*/
298     } scsi;
299 
300     /* statistics information */
301     struct {
302 	unsigned int	queues;
303 	unsigned int	removes;
304 	unsigned int	fins;
305 	unsigned int	reads;
306 	unsigned int	writes;
307 	unsigned int	miscs;
308 	unsigned int	disconnects;
309 	unsigned int	aborts;
310 	unsigned int	resets;
311     } stats;
312 
313     /* queue handling */
314     struct {
315 	Queue_t		issue;			/* issue queue				*/
316 	Queue_t		disconnected;		/* disconnected command queue		*/
317     } queues;
318 
319     /* per-device info */
320     struct {
321 	unsigned char	sync_xfer;		/* synchronous transfer (SBIC value)	*/
322 	syncxfer_t	sync_state;		/* sync xfer negotiation state		*/
323 	unsigned char	disconnect_ok:1;	/* device can disconnect		*/
324     } device[8];
325     unsigned long	busyluns[64 / sizeof(unsigned long)];/* array of bits indicating LUNs busy	*/
326 
327     /* DMA info */
328     struct {
329 	unsigned int	free_addr;		/* next free address			*/
330 	unsigned int	start_addr;		/* start address of current transfer	*/
331 	dmadir_t	direction;		/* dma direction			*/
332 	unsigned int	transferred;		/* number of bytes transferred		*/
333 	unsigned int	xfer_start;		/* scheduled DMA transfer start		*/
334 	unsigned int	xfer_length;		/* scheduled DMA transfer length	*/
335 	char		*xfer_ptr;		/* pointer to area			*/
336 	unsigned char	xfer_required:1;	/* set if we need to transfer something	*/
337 	unsigned char	xfer_setup:1;		/* set if DMA is setup			*/
338 	unsigned char	xfer_done:1;		/* set if DMA reached end of BH list	*/
339     } dma;
340 
341     /* card info */
342     struct {
343 	unsigned char	page_reg;		/* current setting of page reg		*/
344     } card;
345 
346     unsigned char status_ptr[9];
347     struct status_entry status[9][STATUS_BUFFER_SIZE];
348 } AS_Host;
349 
350 #endif /* ACORNSCSI_H */
351