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Searched refs:STG_READ_REG (Results 1 – 5 of 5) sorted by relevance

/linux-6.1.9/drivers/video/fbdev/kyro/
DSTG4000Ramdac.c35 tmp = STG_READ_REG(SoftwareReset); in InitialiseRamdac()
43 tmp = STG_READ_REG(DACPixelFormat); in InitialiseRamdac()
76 tmp = STG_READ_REG(DACPrimSize); in InitialiseRamdac()
90 tmp = STG_READ_REG(DACPLLMode); in InitialiseRamdac()
97 tmp = STG_READ_REG(DACPrimAddress); in InitialiseRamdac()
103 tmp = STG_READ_REG(DACCursorCtrl); in InitialiseRamdac()
107 tmp = STG_READ_REG(DACCursorAddr); in InitialiseRamdac()
112 tmp = STG_READ_REG(DACVidWinStart); in InitialiseRamdac()
117 tmp = STG_READ_REG(DACVidWinEnd); in InitialiseRamdac()
123 tmp = STG_READ_REG(DACBorderColor); in InitialiseRamdac()
[all …]
DSTG4000VTG.c23 tmp = STG_READ_REG(SoftwareReset); in DisableVGA()
33 tmp = STG_READ_REG(SoftwareReset); in DisableVGA()
43 tmp = (STG_READ_REG(DACSyncCtrl)) | SET_BIT(0) | SET_BIT(2); in StopVTG()
53 tmp = ((STG_READ_REG(DACSyncCtrl)) | SET_BIT(31)); in StartVTG()
119 tmp = STG_READ_REG(DACHorTim1); in SetupVTG()
125 tmp = STG_READ_REG(DACHorTim2); in SetupVTG()
131 tmp = STG_READ_REG(DACHorTim3); in SetupVTG()
138 tmp = STG_READ_REG(DACVerTim1); in SetupVTG()
144 tmp = STG_READ_REG(DACVerTim2); in SetupVTG()
150 tmp = STG_READ_REG(DACVerTim3); in SetupVTG()
[all …]
DSTG4000OverlayDevice.c84 tmp = STG_READ_REG(DACOverlayAddr); in ResetOverlayRegisters()
90 tmp = STG_READ_REG(DACOverlayUAddr); in ResetOverlayRegisters()
95 tmp = STG_READ_REG(DACOverlayVAddr); in ResetOverlayRegisters()
100 tmp = STG_READ_REG(DACOverlaySize); in ResetOverlayRegisters()
110 tmp = STG_READ_REG(DACPixelFormat); in ResetOverlayRegisters()
116 tmp = STG_READ_REG(DACVerticalScal); in ResetOverlayRegisters()
123 tmp = STG_READ_REG(DACHorizontalScal); in ResetOverlayRegisters()
133 tmp = STG_READ_REG(DACBlendCtrl); in ResetOverlayRegisters()
176 tmp = STG_READ_REG(DACOverlayAddr); in CreateOverlaySurface()
206 tmp = STG_READ_REG(DACOverlayUAddr); in CreateOverlaySurface()
[all …]
DSTG4000InitDevice.c251 tmp = STG_READ_REG(Thread0Enable); in SetCoreClockPLL()
256 tmp = STG_READ_REG(Thread1Enable); in SetCoreClockPLL()
314 tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0)); in SetCoreClockPLL()
318 tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0)); in SetCoreClockPLL()
DSTG4000Reg.h25 #define STG_READ_REG(reg) (readl(&pSTGReg->reg)) macro
28 #define STG_READ_REG(reg) (pSTGReg->reg) macro