Searched refs:SOC15_REG_ENTRY_OFFSET (Results 1 – 7 of 7) sorted by relevance
382 ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(init_regs[i]) in gfx_v9_4_2_run_shader()1509 WREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_query_sram_edc_count()1514 data = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_query_sram_edc_count()1525 WREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_query_sram_edc_count()1612 WREG32(SOC15_REG_ENTRY_OFFSET(blk->idx_reg), j); in gfx_v9_4_2_query_utc_edc_count()1616 WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg), in gfx_v9_4_2_query_utc_edc_count()1621 data = RREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg)); in gfx_v9_4_2_query_utc_edc_count()1631 WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg), in gfx_v9_4_2_query_utc_edc_count()1683 value = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_2_reset_ea_err_status()1686 WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), value); in gfx_v9_4_2_reset_ea_err_status()[all …]
91 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.… macro
1256 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i])); in mmhub_v1_7_query_ras_error_count()1273 WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0); in mmhub_v1_7_reset_ras_error_count()1296 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i])); in mmhub_v1_7_query_ras_error_status()1315 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( in mmhub_v1_7_reset_ras_error_status()1319 WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]), in mmhub_v1_7_reset_ras_error_status()
887 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_query_ras_error_count()921 RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_reset_ras_error_count()1013 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET( in gfx_v9_4_query_ras_error_status()
756 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); in mmhub_v1_0_query_ras_error_count()774 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i])); in mmhub_v1_0_reset_ras_error_count()
1611 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i])); in mmhub_v9_4_query_ras_error_count()1628 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i])); in mmhub_v9_4_reset_ras_error_count()1653 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_err_status_regs[i])); in mmhub_v9_4_query_ras_error_status()
4437 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) in gfx_v9_0_do_edc_gpr_workarounds()4465 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) in gfx_v9_0_do_edc_gpr_workarounds()4493 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) in gfx_v9_0_do_edc_gpr_workarounds()6486 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); in gfx_v9_0_reset_ras_error_count()6549 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); in gfx_v9_0_query_ras_error_count()