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Searched refs:SKL_ADSP_REG_CL_SD_CTL (Results 1 – 2 of 2) sorted by relevance

/linux-6.1.9/sound/soc/intel/skylake/
Dskl-sst-cldma.c35 SKL_ADSP_REG_CL_SD_CTL, in skl_cldma_stream_run()
42 val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) & in skl_cldma_stream_run()
60 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, in skl_cldma_stream_clear()
62 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, in skl_cldma_stream_clear()
64 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, in skl_cldma_stream_clear()
66 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, in skl_cldma_stream_clear()
119 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, in skl_cldma_setup_controller()
121 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, in skl_cldma_setup_controller()
123 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, in skl_cldma_setup_controller()
125 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL, in skl_cldma_setup_controller()
Dskl-sst-cldma.h27 #define SKL_ADSP_REG_CL_SD_CTL (HDA_ADSP_LOADER_BASE + 0x00) macro